diff mbox series

[V1,1/1] mmc:sdhci-pci-o2micro: Fix SDR50 mode timing issue

Message ID 20230223120450.16858-1-fredaibayhubtech@126.com (mailing list archive)
State New, archived
Headers show
Series [V1,1/1] mmc:sdhci-pci-o2micro: Fix SDR50 mode timing issue | expand

Commit Message

fredaibayhubtech@126.com Feb. 23, 2023, 12:04 p.m. UTC 
From: Fred <fred.ai@bayhubtech.com>

Change SDR50 mode clock source from DLL output clock to PLL open clock
1.HS200 and SDR104 mode select DLL output clock
2.SDR50 mode select PLL open clock

Signed-off-by: Fred <fred.ai@bayhubtech.com>
---
Change in V1
SDR50 mode select PLL open clock as its clock source.
---
 drivers/mmc/host/sdhci-pci-o2micro.c | 30 +++++++++++++++-------------
 1 file changed, 16 insertions(+), 14 deletions(-)

Comments

Fred Ai(WH) March 6, 2023, 2:22 a.m. UTC | #1 
Best regards!

I am the software engineer of the Bayhub Electronic Technology Co. I am writing to you to inquire about the progress of this patch.

Title “[PATCH V1 1/1] mmc:sdhci-pci-o2micro: Fix SDR50 mode timing issue” 
Time :February 3rd, 2023. 

Looking forward to your reply!

Best regards!
Fred

> -----邮件原件-----
> 发件人: fredaibayhubtech@126.com <fredaibayhubtech@126.com>
> 发送时间: 2023年2月23日 20:05
> 收件人: adrian_hunter@intel.com; ulf.hansson@linaro.org;
> linux-mmc@vger.kernel.org; linux.kernel@vger.kernel.org
> 抄送: Shaper Liu (WH) <shaper.liu@bayhubtech.com>; Chevron Li (WH)
> <chevron.li@bayhubtech.com>; XiaoGuang Yu (WH)
> <xiaoguang.yu@bayhubtech.com>; Shirley Her(SC)
> <shirley.her@bayhubtech.com>; Fred Ai(WH) <fred.ai@bayhubtech.com>
> 主题: [PATCH V1 1/1] mmc:sdhci-pci-o2micro: Fix SDR50 mode timing issue
> 
> From: Fred <fred.ai@bayhubtech.com>
> 
> Change SDR50 mode clock source from DLL output clock to PLL open clock
> 1.HS200 and SDR104 mode select DLL output clock
> 2.SDR50 mode select PLL open clock
> 
> Signed-off-by: Fred <fred.ai@bayhubtech.com>
> ---
> Change in V1
> SDR50 mode select PLL open clock as its clock source.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 30 +++++++++++++++-------------
>  1 file changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c
> b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 98cadff47b2b..620f52ad9667 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -339,22 +339,24 @@ static int sdhci_o2_execute_tuning(struct mmc_host
> *mmc, u32 opcode)
>  	reg_val &= ~SDHCI_CLOCK_CARD_EN;
>  	sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
> 
> -	/* UnLock WP */
> -	pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -	scratch_8 &= 0x7f;
> -	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> -
> -	/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> -	pci_read_config_dword(chip->pdev,
> O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> -	reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> -	reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> -	pci_write_config_dword(chip->pdev,
> O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
> +	if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +		(host->timing == MMC_TIMING_UHS_SDR104)) {
> +		/* UnLock WP */
> +		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +		scratch_8 &= 0x7f;
> +		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> 
> -	/* Lock WP */
> -	pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -	scratch_8 |= 0x80;
> -	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +		/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> +		pci_read_config_dword(chip->pdev,
> O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> +		reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> +		reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> +		pci_write_config_dword(chip->pdev,
> O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
> 
> +		/* Lock WP */
> +		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +		scratch_8 |= 0x80;
> +		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +	}
>  	/* Start clk */
>  	reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>  	reg_val |= SDHCI_CLOCK_CARD_EN;
> --
> 2.37.2
Ulf Hansson March 9, 2023, 1:56 p.m. UTC | #2 
+ Adrian (corrected the email)

On Thu, 23 Feb 2023 at 13:05, <fredaibayhubtech@126.com> wrote:
>
> From: Fred <fred.ai@bayhubtech.com>
>
> Change SDR50 mode clock source from DLL output clock to PLL open clock
> 1.HS200 and SDR104 mode select DLL output clock
> 2.SDR50 mode select PLL open clock
>
> Signed-off-by: Fred <fred.ai@bayhubtech.com>

Looks like you posted this to an incorrect email to Adrian, perhaps
re-post to include him.

Kind regards
Uffe

> ---
> Change in V1
> SDR50 mode select PLL open clock as its clock source.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 30 +++++++++++++++-------------
>  1 file changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 98cadff47b2b..620f52ad9667 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -339,22 +339,24 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>         reg_val &= ~SDHCI_CLOCK_CARD_EN;
>         sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
>
> -       /* UnLock WP */
> -       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -       scratch_8 &= 0x7f;
> -       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> -
> -       /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> -       pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> -       reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> -       reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> -       pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
> +       if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +               (host->timing == MMC_TIMING_UHS_SDR104)) {
> +               /* UnLock WP */
> +               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +               scratch_8 &= 0x7f;
> +               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
>
> -       /* Lock WP */
> -       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -       scratch_8 |= 0x80;
> -       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +               /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> +               pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> +               reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> +               reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> +               pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
>
> +               /* Lock WP */
> +               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +               scratch_8 |= 0x80;
> +               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +       }
>         /* Start clk */
>         reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>         reg_val |= SDHCI_CLOCK_CARD_EN;
> --
> 2.37.2
>
Adrian Hunter March 10, 2023, 11:42 a.m. UTC | #3 
On 23/02/23 14:04, fredaibayhubtech@126.com wrote:
> From: Fred <fred.ai@bayhubtech.com>
> 
> Change SDR50 mode clock source from DLL output clock to PLL open clock
> 1.HS200 and SDR104 mode select DLL output clock
> 2.SDR50 mode select PLL open clock
> 
> Signed-off-by: Fred <fred.ai@bayhubtech.com>

Seems like it could use a fixes tag? Nevertheless:

Acked-by: Adrian Hunter <adrian.hunter@intel.com>

> ---
> Change in V1
> SDR50 mode select PLL open clock as its clock source.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 30 +++++++++++++++-------------
>  1 file changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 98cadff47b2b..620f52ad9667 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -339,22 +339,24 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>  	reg_val &= ~SDHCI_CLOCK_CARD_EN;
>  	sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
>  
> -	/* UnLock WP */
> -	pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -	scratch_8 &= 0x7f;
> -	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> -
> -	/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> -	pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> -	reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> -	reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> -	pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
> +	if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +		(host->timing == MMC_TIMING_UHS_SDR104)) {
> +		/* UnLock WP */
> +		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +		scratch_8 &= 0x7f;
> +		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
>  
> -	/* Lock WP */
> -	pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -	scratch_8 |= 0x80;
> -	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +		/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> +		pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> +		reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> +		reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> +		pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
>  
> +		/* Lock WP */
> +		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +		scratch_8 |= 0x80;
> +		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +	}
>  	/* Start clk */
>  	reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>  	reg_val |= SDHCI_CLOCK_CARD_EN;
Ulf Hansson March 10, 2023, 3:14 p.m. UTC | #4 
On Thu, 23 Feb 2023 at 13:05, <fredaibayhubtech@126.com> wrote:
>
> From: Fred <fred.ai@bayhubtech.com>
>
> Change SDR50 mode clock source from DLL output clock to PLL open clock
> 1.HS200 and SDR104 mode select DLL output clock
> 2.SDR50 mode select PLL open clock
>
> Signed-off-by: Fred <fred.ai@bayhubtech.com>

Applied for next, thanks!

Perhaps I should move this to the fixes branch and we should add a
fixes and a stable tag too?

Kind regards
Uffe

> ---
> Change in V1
> SDR50 mode select PLL open clock as its clock source.
> ---
>  drivers/mmc/host/sdhci-pci-o2micro.c | 30 +++++++++++++++-------------
>  1 file changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
> index 98cadff47b2b..620f52ad9667 100644
> --- a/drivers/mmc/host/sdhci-pci-o2micro.c
> +++ b/drivers/mmc/host/sdhci-pci-o2micro.c
> @@ -339,22 +339,24 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
>         reg_val &= ~SDHCI_CLOCK_CARD_EN;
>         sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
>
> -       /* UnLock WP */
> -       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -       scratch_8 &= 0x7f;
> -       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> -
> -       /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> -       pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> -       reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> -       reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> -       pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
> +       if ((host->timing == MMC_TIMING_MMC_HS200) ||
> +               (host->timing == MMC_TIMING_UHS_SDR104)) {
> +               /* UnLock WP */
> +               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +               scratch_8 &= 0x7f;
> +               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
>
> -       /* Lock WP */
> -       pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> -       scratch_8 |= 0x80;
> -       pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +               /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
> +               pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
> +               reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
> +               reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
> +               pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
>
> +               /* Lock WP */
> +               pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
> +               scratch_8 |= 0x80;
> +               pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
> +       }
>         /* Start clk */
>         reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>         reg_val |= SDHCI_CLOCK_CARD_EN;
> --
> 2.37.2
>
diff mbox series

Patch

diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c
index 98cadff47b2b..620f52ad9667 100644
--- a/drivers/mmc/host/sdhci-pci-o2micro.c
+++ b/drivers/mmc/host/sdhci-pci-o2micro.c
@@ -339,22 +339,24 @@  static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 	reg_val &= ~SDHCI_CLOCK_CARD_EN;
 	sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
 
-	/* UnLock WP */
-	pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
-	scratch_8 &= 0x7f;
-	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
-
-	/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
-	pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
-	reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
-	reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
-	pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
+	if ((host->timing == MMC_TIMING_MMC_HS200) ||
+		(host->timing == MMC_TIMING_UHS_SDR104)) {
+		/* UnLock WP */
+		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
+		scratch_8 &= 0x7f;
+		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
 
-	/* Lock WP */
-	pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
-	scratch_8 |= 0x80;
-	pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
+		/* Set pcr 0x354[16] to choose dll clock, and set the default phase */
+		pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &reg_val);
+		reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
+		reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
+		pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
 
+		/* Lock WP */
+		pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
+		scratch_8 |= 0x80;
+		pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
+	}
 	/* Start clk */
 	reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
 	reg_val |= SDHCI_CLOCK_CARD_EN;