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Mon, 1 Jul 2024 08:13:11 -0700 From: Krishna Yarlagadda To: , , , , , CC: , , , , , , , , , , , , , Subject: [RFC PATCH V2 06/12] i2c: tegra: split clock initialization code Date: Mon, 1 Jul 2024 20:42:24 +0530 Message-ID: <20240701151231.29425-7-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240701151231.29425-1-kyarlagadda@nvidia.com> References: <20240701151231.29425-1-kyarlagadda@nvidia.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|DM4PR12MB7525:EE_ X-MS-Office365-Filtering-Correlation-Id: 9bad22a1-d8d9-4bfa-a7c5-08dc99e05ded X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: pSQQOqOs2t/nvwRVj94Al1+idUNNZxt+1uvlmo19XukNve3IC+NJ5Z9dzlnVSJv/OGpuVDXLOMWDCQgWDs1M/7vrtn16hLeWtKP9k9n7yNecDFKc+MyNN5H1HBYxnRorvJAXlmhdehe6H76ZA/AjUqjQ2V7vhDsJyZf/7J5T7URSCHb5kYMh+LBFW2qhomzYaOoRScNaWM0Grce5p2vCn6kabE6Ted0GOZeYaOVfOSaWe4emb3o2s9YpfznZp4KEiFwaMZ9rQ9yI/6RXPe3eM5ZK0Gvf0zbEBi0bV/ETl5HZvD3KGBAJTiS9ip1+Pfs0U3aaEPgwd3NUTzdFSqIvUT/Xd3JYMp7N1+29yOksvbxOSASuyuVhfrcgffqMUolkWbxFMfcMQ3fXL0RsXQ+8AXljWc7wPKbCL3aWlSnqm7b5biT5T2Pos7B0vJOmFEynxUfJXWTFsScstVzZOrzktECXDALa12aD4CVhRK4DwOMDWnj95LwWUnRZqKjKib9F/3Q6Nb7KdR2Shw7d2KrVnpyIKxSQts26EiDxADXyhYEzFII8jPYp0iXaqlG/HawnviIY8yQIYuiDCb73OgreEYbUVO8BHESVPUTA245E8NMkeKGyXb0Cjysn8BjIOaqqCG0+rcfSN3GxwEswmNoVnHb85LiJa2kwtvqgnrYVn2tkSbmGCy+rIbZkDUUUZEu0PZrxLJewsavGFkA73sCFTmYcqg9urZ+PbYygYW20KXp6liu5xqpaTgmVTDlEQcvrOHFQQPj1lpcax3UWJ9oYAVqxEoRo7+EBMCFfkfk7kOhSI6zpR8q1L6t6Fq3ZcvPowlvdzvB1iTBqrAChOvYQwdHP5iawiQVLtAOzuV7SmZ13yrkihJOkbnaBgJW5SCDNsyViJ7sud01oYAsgbS2/lhugZ9fKMmLjr5IOGsLff1OwIUp3xSZWs2UnG2wfvIlv2Bq1yF820rIRIElmH3PvTM15urz9qq0TXr/0wIZlhbTnkZJHm1ov3+33mkScryLMg+AsXNo/9dYOLMYHfeqcWq/oBpN0fkBdEUda47HefQbjVQDlYY6gFchBBy5HsW4+71YDU5ANuOkqJNFTHuejk/t6g/tfxZbS06imBcxLcnP19et1S7kbFXU+FpHXcOyPsRwi2f4w9fLlaFLyUzp/aDTKBJhaQLuCf8QN1bJxf8/km+0EuB7ElRA0n/rBTGDzldAKHRv9+nZVsXDWCHaRBJPCmp0braHMXr5sdizXRqnHxO8ZUuYI/9lODvhkJNvZ9FUF8Bs4IEnKfzUvh8L+wjqARsxPksMHiY4FdHmg0skuATxCvUq0JE+ZhvEQJ+GtX2xPXfAf5ABBTpIIhhdLrwLzUp0r4iUTa3P/U5fqfO8BTjOf5RVUvaQ6jZgHvadIC3SluzbbXLlM9+EqJHfoBAiGWQn+n2EQAzuoSXy2qVGx8D/c5YwtFx9kc+gNCPwY X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2024 15:13:30.5472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9bad22a1-d8d9-4bfa-a7c5-08dc99e05ded X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7525 Add new methods for setting clock parameters and setting clock divisor. Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 127 ++++++++++++++++++++------------- 1 file changed, 77 insertions(+), 50 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 85b31edc558d..b3dc2603db35 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -604,12 +604,83 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) return 0; } +static void tegra_i2c_set_clk_params(struct tegra_i2c_dev *i2c_dev) +{ + u32 val, clk_divisor, tsu_thd, tlow, thigh, non_hs_mode; + + switch (i2c_dev->timings.bus_freq_hz) { + case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: + default: + tlow = i2c_dev->hw->tlow_fast_fastplus_mode; + thigh = i2c_dev->hw->thigh_fast_fastplus_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; + + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) + non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; + else + non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; + break; + + case 0 ... I2C_MAX_STANDARD_MODE_FREQ: + tlow = i2c_dev->hw->tlow_std_mode; + thigh = i2c_dev->hw->thigh_std_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; + non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; + break; + } + + /* make sure clock divisor programmed correctly */ + clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, + i2c_dev->hw->clk_divisor_hs_mode) | + FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); + i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); + + if (i2c_dev->hw->has_interface_timing_reg) { + val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); + } + + /* + * Configure setup and hold times only when tsu_thd is non-zero. + * Otherwise, preserve the chip default values. + */ + if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) + i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); +} + +static int tegra_i2c_set_div_clk(struct tegra_i2c_dev *i2c_dev) +{ + u32 clk_multiplier, tlow, thigh, non_hs_mode; + u32 timing, clk_divisor; + int err; + + timing = i2c_readl(i2c_dev, I2C_INTERFACE_TIMING_0); + + tlow = FIELD_GET(I2C_INTERFACE_TIMING_TLOW, timing); + thigh = FIELD_GET(I2C_INTERFACE_TIMING_THIGH, timing); + + clk_divisor = i2c_readl(i2c_dev, I2C_CLK_DIVISOR); + + non_hs_mode = FIELD_GET(I2C_CLK_DIVISOR_STD_FAST_MODE, clk_divisor); + + clk_multiplier = (thigh + tlow + 2) * (non_hs_mode + 1); + + err = clk_set_rate(i2c_dev->div_clk, + i2c_dev->timings.bus_freq_hz * clk_multiplier); + if (err) { + dev_err(i2c_dev->dev, "failed to set div_clk rate: %d\n", err); + return err; + } + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { - u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; + u32 val; + int err; acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); - struct i2c_timings *t = &i2c_dev->timings; - int err; /* * The reset shouldn't ever fail in practice. The failure will be a @@ -641,54 +712,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); - switch (t->bus_freq_hz) { - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: - default: - tlow = i2c_dev->hw->tlow_fast_fastplus_mode; - thigh = i2c_dev->hw->thigh_fast_fastplus_mode; - tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; - - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) - non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; - else - non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; - break; - - case 0 ... I2C_MAX_STANDARD_MODE_FREQ: - tlow = i2c_dev->hw->tlow_std_mode; - thigh = i2c_dev->hw->thigh_std_mode; - tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; - non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; - break; - } - - /* make sure clock divisor programmed correctly */ - clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, - i2c_dev->hw->clk_divisor_hs_mode) | - FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); - i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); - - if (i2c_dev->hw->has_interface_timing_reg) { - val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | - FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); - i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); - } - - /* - * Configure setup and hold times only when tsu_thd is non-zero. - * Otherwise, preserve the chip default values. - */ - if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) - i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); - - clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); - - err = clk_set_rate(i2c_dev->div_clk, - t->bus_freq_hz * clk_multiplier); - if (err) { - dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); + tegra_i2c_set_clk_params(i2c_dev); + err = tegra_i2c_set_div_clk(i2c_dev); + if (err) return err; - } if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);