From patchwork Fri Jan 21 19:36:01 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 496301 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p0LJZR6C009354 for ; Fri, 21 Jan 2011 19:36:06 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754900Ab1AUTgF (ORCPT ); Fri, 21 Jan 2011 14:36:05 -0500 Received: from na3sys009aog115.obsmtp.com ([74.125.149.238]:42100 "HELO na3sys009aog115.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1754859Ab1AUTgF convert rfc822-to-8bit (ORCPT ); Fri, 21 Jan 2011 14:36:05 -0500 Received: from source ([65.219.4.129]) (using TLSv1) by na3sys009aob115.postini.com ([74.125.148.12]) with SMTP ID DSNKTTngJFXtHottD1E0dNZeJiH7lEbJKJFG@postini.com; Fri, 21 Jan 2011 11:36:05 PST Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by SC-OWA01.marvell.com ([10.93.76.21]) with mapi; Fri, 21 Jan 2011 11:36:02 -0800 From: Philip Rakity To: "linux-mmc@vger.kernel.org" CC: Mark Brown Date: Fri, 21 Jan 2011 11:36:01 -0800 Subject: [PATCH] sdhci: add support for hardware clock gating Thread-Topic: [PATCH] sdhci: add support for hardware clock gating Thread-Index: Acu5om+P0qjV3q+zSCmIhWQ0C076Iw== Message-ID: <219B8EAC-935D-4AFD-8AF0-353D4CE6EEB6@marvell.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 21 Jan 2011 19:36:06 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c index 2a6b156..b31d3d5 100644 --- a/drivers/mmc/host/sdhci-pxa.c +++ b/drivers/mmc/host/sdhci-pxa.c @@ -138,10 +138,23 @@ static void platform_reset_exit(struct sdhci_host *host, u8 mask) } } +#ifdef CONFIG_MMC_CLKGATE +static void platform_hw_clk_gate(struct sdhci_host *host) +{ + int enable; + + enable = host->mmc->clk_gated; + programFIFO(host, enable); +} +#endif + static struct sdhci_ops sdhci_pxa_ops = { .get_f_max_clock = NULL, .set_signaling_voltage = set_signaling_voltage, .platform_reset_exit = platform_reset_exit, +#ifdef CONFIG_MMC_CLKGATE + .platform_hw_clk_gate = platform_hw_clk_gate, +#endif }; /*****************************************************************************\ @@ -209,8 +222,11 @@ static int __devinit sdhci_pxa_probe(struct platform_device *pdev) host->irq = irq; host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; - /* enable mmc bus width testing */ +#ifdef CONFIG_MMC_CLKGATE + host->mmc->caps |= MMC_CAP_HW_CLOCK_GATING | MMC_CAP_BUS_WIDTH_TEST; +#else host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; +#endif /* If slot design supports 8 bit data, indicate this to MMC. */ if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)