From patchwork Wed Dec 8 00:20:36 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 384682 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB80UxuG009619 for ; Wed, 8 Dec 2010 00:32:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754660Ab0LHAcE (ORCPT ); Tue, 7 Dec 2010 19:32:04 -0500 Received: from na3sys009aog102.obsmtp.com ([74.125.149.69]:39377 "HELO na3sys009aog102.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1754013Ab0LHAcE convert rfc822-to-8bit (ORCPT ); Tue, 7 Dec 2010 19:32:04 -0500 Received: from source ([65.219.4.130]) (using TLSv1) by na3sys009aob102.postini.com ([74.125.148.12]) with SMTP ID DSNKTP7R/c+kBo+Tqweqon+mtLnJJdj0643s@postini.com; Tue, 07 Dec 2010 16:32:03 PST Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by sc-owa02.marvell.com ([10.93.76.22]) with mapi; Tue, 7 Dec 2010 16:20:38 -0800 From: Philip Rakity To: Chris Ball CC: "linux-mmc@vger.kernel.org" , Nicolas Pitre , Mark Brown Date: Tue, 7 Dec 2010 16:20:36 -0800 Subject: [PATCH V3 3/3 ] mmc: add support for H/W clock gating of SD controller (resend) Thread-Topic: [PATCH V3 3/3 ] mmc: add support for H/W clock gating of SD controller (resend) Thread-Index: AcuWbb0/amDR2QKKQseg7G2iDp1OjA== Message-ID: <4024F858-A92E-4DCC-8615-528BF48939D2@marvell.com> References: <5017B261-76AC-428D-BAC2-8E1BBEB09A49@marvell.com> <20101208001618.GA3338@void.printf.net> In-Reply-To: <20101208001618.GA3338@void.printf.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Wed, 08 Dec 2010 00:32:05 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c index 5a61208..5cf47fd 100644 --- a/drivers/mmc/host/sdhci-pxa.c +++ b/drivers/mmc/host/sdhci-pxa.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "sdhci.h" #define DRIVER_NAME "sdhci-pxa" @@ -46,10 +47,27 @@ struct sdhci_pxa { * SDHCI core callbacks * * * \*****************************************************************************/ +#ifdef CONFIG_MMC_CLKGATE +static void hardware_clk_gating(struct sdhci_host *host) +{ + unsigned short tmp; + int enable; + + enable = host->mmc->clk_gated; + tmp = readw(host->ioaddr + SD_FIFO_PARAM); + + if (enable) + tmp &= ~DIS_PAD_SD_CLK_GATE; + else + tmp |= DIS_PAD_SD_CLK_GATE; + + writew(tmp, host->ioaddr + SD_FIFO_PARAM); +} +#endif + static void set_clock(struct sdhci_host *host, unsigned int clock) { struct sdhci_pxa *pxa = sdhci_priv(host); - u32 tmp = 0; if (clock == 0) { if (pxa->clk_enable) { @@ -58,11 +76,6 @@ static void set_clock(struct sdhci_host *host, unsigned int clock) } } else { if (0 == pxa->clk_enable) { - if (pxa->pdata->flags & PXA_FLAG_DISABLE_CLOCK_GATING) { - tmp = readl(host->ioaddr + SD_FIFO_PARAM); - tmp |= DIS_PAD_SD_CLK_GATE; - writel(tmp, host->ioaddr + SD_FIFO_PARAM); - } clk_enable(pxa->clk); pxa->clk_enable = 1; } @@ -71,6 +84,9 @@ static void set_clock(struct sdhci_host *host, unsigned int clock) static struct sdhci_ops sdhci_pxa_ops = { .set_clock = set_clock, +#ifdef CONFIG_MMC_CLKGATE + .platform_hw_clk_gate = hardware_clk_gating, +#endif }; /*****************************************************************************\ @@ -145,6 +161,11 @@ static int __devinit sdhci_pxa_probe(struct platform_device *pdev) if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT) host->mmc->caps |= MMC_CAP_8_BIT_DATA; +#ifdef CONFIG_MMC_CLKGATE + if (cpu_is_mmp2()) + host->mmc->caps |= MMC_CAP_HW_CLOCK_GATING; +#endif + ret = sdhci_add_host(host); if (ret) { dev_err(&pdev->dev, "failed to add host\n");