From patchwork Fri May 13 06:05:07 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Nikam X-Patchwork-Id: 781772 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p4D65GBo010741 for ; Fri, 13 May 2011 06:05:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751182Ab1EMGFP (ORCPT ); Fri, 13 May 2011 02:05:15 -0400 Received: from hqemgate03.nvidia.com ([216.228.121.140]:19799 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750874Ab1EMGFO convert rfc822-to-8bit (ORCPT ); Fri, 13 May 2011 02:05:14 -0400 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 12 May 2011 23:14:12 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Thu, 12 May 2011 23:05:11 -0700 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Thu, 12 May 2011 23:05:11 -0700 Received: from bgemhub01.nvidia.com (10.25.128.13) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.2.254.0; Thu, 12 May 2011 23:05:11 -0700 Received: from BGMAIL02.nvidia.com ([10.25.128.18]) by bgemhub01.nvidia.com ([10.25.128.13]) with mapi; Fri, 13 May 2011 11:35:07 +0530 From: Sachin Nikam To: "'Arindam Nath'" , "cjb@laptop.org" CC: "linux-mmc@vger.kernel.org" , "prakity@marvell.com" , "zhangfei.gao@gmail.com" Importance: high X-Priority: 1 Date: Fri, 13 May 2011 11:35:07 +0530 Subject: RE: [PATCH v2 4/4] mmc add support for eMMC Dual Data Rate Thread-Topic: [PATCH v2 4/4] mmc add support for eMMC Dual Data Rate Thread-Index: AcwRMX6BRQDImVnxQIuwJhRpgQFyLgAAimxQ Message-ID: <723849F6A4B5A3408299DF1FFE37CA776C09CFC1FB@BGMAIL02.nvidia.com> References: <1305265638-1572-1-git-send-email-arindam.nath@amd.com> <1305265638-1572-5-git-send-email-arindam.nath@amd.com> In-Reply-To: <1305265638-1572-5-git-send-email-arindam.nath@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Content-Language: en-US Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 13 May 2011 06:05:16 +0000 (UTC) Hello Folks, Sorry for interruption. I wanted to know when and which version of kernel mmc driver will have SD 4.0(UHS-II) support? Regards, Sachin Nikam. NVIDIA. -----Original Message----- From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-owner@vger.kernel.org] On Behalf Of Arindam Nath Sent: Friday, May 13, 2011 11:17 AM To: cjb@laptop.org Cc: linux-mmc@vger.kernel.org; prakity@marvell.com; zhangfei.gao@gmail.com; Arindam Nath Subject: [PATCH v2 4/4] mmc add support for eMMC Dual Data Rate From: Philip Rakity eMMC voltage change not required for 1.8V. 3.3V and 1.8V vcc are capable of doing DDR. vccq of 1.8v is not required. Signed-off-by: Philip Rakity Reviewed-by: Arindam Nath --- drivers/mmc/core/core.c | 14 ++------------ drivers/mmc/core/core.h | 2 -- drivers/mmc/core/mmc.c | 35 ++++++++++++++++++++++++++++++----- include/linux/mmc/host.h | 1 + 4 files changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 580fe82..43ca596 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -718,22 +718,12 @@ void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode) } /* - * Change data bus width and DDR mode of a host. - */ -void mmc_set_bus_width_ddr(struct mmc_host *host, unsigned int width, - unsigned int ddr) -{ - host->ios.bus_width = width; - host->ios.ddr = ddr; - mmc_set_ios(host); -} - -/* * Change data bus width of a host. */ void mmc_set_bus_width(struct mmc_host *host, unsigned int width) { - mmc_set_bus_width_ddr(host, width, MMC_SDR_MODE); + host->ios.bus_width = width; + mmc_set_ios(host); } /** diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h index 53d23c2..d9411ed 100644 --- a/drivers/mmc/core/core.h +++ b/drivers/mmc/core/core.h @@ -38,8 +38,6 @@ void mmc_ungate_clock(struct mmc_host *host); void mmc_set_ungated(struct mmc_host *host); void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode); void mmc_set_bus_width(struct mmc_host *host, unsigned int width); -void mmc_set_bus_width_ddr(struct mmc_host *host, unsigned int width, - unsigned int ddr); u32 mmc_select_voltage(struct mmc_host *host, u32 ocr); int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, bool cmd11); diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index a2c795e..0433fe6 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -20,6 +20,7 @@ #include "core.h" #include "bus.h" #include "mmc_ops.h" +#include "sd_ops.h" static const unsigned int tran_exp[] = { 10000, 100000, 1000000, 10000000, @@ -633,10 +634,14 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, */ if (mmc_card_highspeed(card)) { if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) - && (host->caps & (MMC_CAP_1_8V_DDR))) + && ((host->caps & (MMC_CAP_1_8V_DDR | + MMC_CAP_UHS_DDR50)) + == (MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50))) ddr = MMC_1_8V_DDR_MODE; else if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_2V) - && (host->caps & (MMC_CAP_1_2V_DDR))) + && ((host->caps & (MMC_CAP_1_2V_DDR | + MMC_CAP_UHS_DDR50)) + == (MMC_CAP_1_2V_DDR | MMC_CAP_UHS_DDR50))) ddr = MMC_1_2V_DDR_MODE; } @@ -670,8 +675,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, ext_csd_bits[idx][0], 0); if (!err) { - mmc_set_bus_width_ddr(card->host, - bus_width, MMC_SDR_MODE); + mmc_set_bus_width(card->host, bus_width); /* * If controller can't handle bus width test, * use the highest bus width to maintain @@ -697,8 +701,29 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr, 1 << bus_width, ddr); goto free_card; } else if (ddr) { + /* + * eMMC cards can support 3.3V to 1.2V i/o (vccq) + * signaling. + * + * EXT_CSD_CARD_TYPE_DDR_1_8V means 3.3V or 1.8V vccq. + * + * 1.8V vccq at 3.3V core voltage (vcc) is not required + * in the JEDEC spec for DDR. + * + * Do not force change in vccq since we are obviously + * working and no change to vccq is needed. + * + * WARNING: eMMC rules are NOT the same as SD DDR + */ + if (ddr == EXT_CSD_CARD_TYPE_DDR_1_2V) { + err = mmc_set_signal_voltage(host, + MMC_SIGNAL_VOLTAGE_120, 0); + if (err) + goto err; + } mmc_card_set_ddr_mode(card); - mmc_set_bus_width_ddr(card->host, bus_width, ddr); + mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50); + mmc_set_bus_width(card->host, bus_width); } } diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 6716bd1..de32e6a 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -66,6 +66,7 @@ struct mmc_ios { #define MMC_SIGNAL_VOLTAGE_330 0 #define MMC_SIGNAL_VOLTAGE_180 1 +#define MMC_SIGNAL_VOLTAGE_120 2 unsigned char drv_type; /* driver type (A, B, C, D) */