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Mon, 26 Aug 2024 14:26:31 -0700 From: Liming Sun To: Adrian Hunter , Ulf Hansson , David Thompson CC: Liming Sun , , Subject: [PATCH v1 1/1] mmc: sdhci-of-dwcmshc: Add hw_reset() support for BlueField-3 SoC Date: Mon, 26 Aug 2024 17:26:27 -0400 Message-ID: <73703c853e36f3cd61114e4ac815926d94a1a802.1724695127.git.limings@nvidia.com> X-Mailer: git-send-email 2.30.1 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37C:EE_|SA1PR12MB5613:EE_ X-MS-Office365-Filtering-Correlation-Id: 510c8bb9-546a-4cec-75bd-08dcc615cbd2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: iGza6bZmEL82Z6NcrhQfYRBtV6g5iXKhC4FyPkDy9xEZVPBBthCN6hSzqlryuQFmzI+v3U2sEAvciT2IATE7lJ6fG0U+PbhG0F9vIgm89S4kEsmezulNsUka2AbaKHryCclr2/MUwmx9SOf1sUvWPBrcGBUn1Sa1MwOeWD8KsaQwTyQlVyZcuXjvKcTSI2e3PA0anwWeaJQKZ2M+FpPPtj3TnhgwQ0zN0OrKUC25w7wb7qf64RAPmvhG/+vnqaIb5LbFCigvKxvEEnSpQ6+H7itGdIiJ71D2K8ZK9Y5xqs+6M6IKMTyy16Gxy1m6vrfkGLROZ7NOe0vth+QbOjBHpbLqjsWFsegnO7m9Tb1e2MFwnW9yEGTiWpLCd8QTNucEDS/U1i3HesbngqBrCdcrP2ETA7t7bQbCfUi7xiXjR43cCnvotFnWbM09edJPELP3pcpTq5b+D0ZQl/r3KGM0E0iLhzauQtnQ13pgTZgLHOaVPB0OIFgj11hCL9LfD5R18LFqaicVTnqWmGp4oAtplTYtaoSHY3qQ8XNnQRXNl2uu4kmuiIR2zzTWWqt8lE+mIbUPAOVF6lWGT+Cg7MKO0wUhCHLYQFo2HvffK+wFOetKvwfhDd8GOfQd+hV/b/l5fNIqQFHcXcBPtGtGFchUyb+WjtErNg9wGSH/30Nf1xIqa+waOqN5GmEha84rJ3Q7+P0PhBzOIV2sBHaZqpTNjbcfNNXpV2yfVGgVbAsCPR05r5WkVVPrLKW3CPRIYAWpXAiHwGKOaiCXxMg82HEu3aIVuHPeN1RxE/h5ra0/R0jt8NiBnFrTHV0xuCmAEJSvE9PK0QDOdxAJNlF4xXHaXetBZ/KIQpG3UZYi1eZkDHirnwP0EaMiRftQUjTW8bFrSpw0guM712Gt1rUWxkcxJDohCk8HqP7+z9XWI9BgfXGdTPn1crEsVygRXXdJ12iSIE8HMSx1EYe0/QbRujJZtCoqKsTZmredL0BRDiHakJ3QT5h5ZS1Xx2LsMfOm7yQMRIzwRD/dXk8Pf4M2yxxZA4EIp6hJoxzMnsfoDNF7h3FW9jzPVwe6aqkXPIl7gcQbUiqCXZbVlJC5uy01prTJJ1tRqguFbkJOzmV+Rpx10P/Vu/jSzrnc3hiyHwcskK8AJ4wC9sjjQLy6DpOr4V0Bg1ai1drEPIZURp1uTa6PzXlncMZswiCoK9jfJKLfzOTyufjCe37qpDRnRV3ZECmIE3FcD16lFYgDJ5qcbjK8k6hvlo3VwAGkF2RuM48hqJq5n335J+QC4BQqsJOATV+20IMXXZTNAUAqwXLfbzc9gsFwzKDIQMYtoZGf4Qy+uqlzhLQDfy3PRauFLgMVKuAdaLR0xN32t4tlhXl+2/BZm7KwdN+LdeLZheE2wwBtdQ31xCxuHytQRyOUKAFaE4sL3i5ZWNpUoFEFK4jTK/7qr2SLkif2lAL1IFZ8exBFxeJy X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Aug 2024 21:26:49.4229 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 510c8bb9-546a-4cec-75bd-08dcc615cbd2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5613 The eMMC RST_N register is implemented as secure register on the BlueField-3 SoC and controlled by TF-A. This commit adds the hw_reset() support which sends an SMC call to TF-A for the eMMC HW reset. Reviewed-by: David Thompson Signed-off-by: Liming Sun --- drivers/mmc/host/sdhci-of-dwcmshc.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index ba8960d8b2d4..3c763e67e4ac 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -201,6 +202,9 @@ SDHCI_TRNS_BLK_CNT_EN | \ SDHCI_TRNS_DMA) +/* SMC call for BlueField-3 eMMC RST_N */ +#define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 + enum dwcmshc_rk_type { DWCMSHC_RK3568, DWCMSHC_RK3588, @@ -1111,6 +1115,29 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { .irq = dwcmshc_cqe_irq_handler, }; +#ifdef CONFIG_ACPI +static void dwcmshc_bf3_hw_reset(struct sdhci_host *host) +{ + struct arm_smccc_res res = { 0 }; + + arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res); + + if (res.a0) + pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); +} + +static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = dwcmshc_set_uhs_signaling, + .get_max_clock = dwcmshc_get_max_clock, + .reset = sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + .irq = dwcmshc_cqe_irq_handler, + .hw_reset = dwcmshc_bf3_hw_reset, +}; +#endif + static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { .set_clock = dwcmshc_rk3568_set_clock, .set_bus_width = sdhci_set_bus_width,