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[v3,1/2] mmc/host/rtsx: Configure SD_CFG2 register in sd_rw_multi

Message ID 8b41e6e8d51049a3e6c9c0db4e53aabe1e82c9c9.1353381810.git.wei_wang@realsil.com.cn (mailing list archive)
State New, archived
Headers show

Commit Message

wei_wang@realsil.com.cn Nov. 20, 2012, 3:24 a.m. UTC 
From: Wei WANG <wei_wang@realsil.com.cn>

For Realtek card reader, internal regsiter SD_CFG2 should be configured
before transferring data.
The default value of SD_CFG2 is proper for writing data. But for reading
sequence, the timing is not good enough. So in some extreme circumstance,
card reader may sample the response data from the card as good even if
the data is wrong. And this will cause the bad consequence.
In the prior version, the value of this register has been calculated,
but forgotten to write back to the internal register.

Signed-off-by: Wei WANG <wei_wang@realsil.com.cn>
Acked-by: Chris Ball <cjb@laptop.org>
---
 drivers/mmc/host/rtsx_pci_sdmmc.c |    1 +
 1 file changed, 1 insertion(+)
diff mbox

Patch

diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c
index 0e934bf..067dd46 100644
--- a/drivers/mmc/host/rtsx_pci_sdmmc.c
+++ b/drivers/mmc/host/rtsx_pci_sdmmc.c
@@ -405,6 +405,7 @@  static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq)
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
 			0x01, RING_BUFFER);
 
+	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2);
 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
 			trans_mode | SD_TRANSFER_START);
 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER,