From patchwork Thu Dec 9 00:18:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philip Rakity X-Patchwork-Id: 392572 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB90IGNI006921 for ; Thu, 9 Dec 2010 00:18:33 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753955Ab0LIASd (ORCPT ); Wed, 8 Dec 2010 19:18:33 -0500 Received: from na3sys009aog103.obsmtp.com ([74.125.149.71]:40432 "HELO na3sys009aog103.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1753905Ab0LIASc convert rfc822-to-8bit (ORCPT ); Wed, 8 Dec 2010 19:18:32 -0500 Received: from source ([65.219.4.130]) (using TLSv1) by na3sys009aob103.postini.com ([74.125.148.12]) with SMTP ID DSNKTQAgV25rkWEt0NbYx9DQ4Yw2xwBMeE8x@postini.com; Wed, 08 Dec 2010 16:18:32 PST Received: from SC-vEXCH3.marvell.com ([10.93.76.133]) by sc-owa02.marvell.com ([10.93.76.22]) with mapi; Wed, 8 Dec 2010 16:18:30 -0800 From: Philip Rakity To: "linux-mmc@vger.kernel.org" CC: Mark Brown , Chris Ball , Nicolas Pitre Date: Wed, 8 Dec 2010 16:18:28 -0800 Subject: [PATCH V4 3/4] mmc: add support for H/W clock gating of SD controller Thread-Topic: [PATCH V4 3/4] mmc: add support for H/W clock gating of SD controller Thread-Index: AcuXNptowughETjGRfCSsknm9cMkoA== Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 09 Dec 2010 00:18:33 +0000 (UTC) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 26a8c09..d8526ae 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -144,7 +144,22 @@ #define SDHCI_ACMD12_ERR 0x3C -/* 3E-3F reserved */ +#define HOST_CTRL_2 0x3E +#define SDCTRL_2_UHS_MODE_SEL_SDR12 0x0000 +#define SDCTRL_2_UHS_MODE_SEL_SDR25 0x0001 +#define SDCTRL_2_UHS_MODE_SEL_SDR50 0x0002 +#define SDCTRL_2_UHS_MODE_SEL_SDR104 0x0003 +#define SDCTRL_2_UHS_MODE_SEL_DDR50 0x0004 +#define SDCTRL_2_UHS_MODE_MASK 7 +#define SDCTRL_2_SDH_V18_EN 0x0008 +#define SDCTRL_2_DRV_STRENGTH_SEL_B 0x0000 +#define SDCTRL_2_DRV_STRENGTH_SEL_A 0x0010 +#define SDCTRL_2_DRV_STRENGTH_SEL_C 0x0020 +#define SDCTRL_2_DRV_STRENGTH_SEL_D 0x0030 +#define SDCTRL_2_EXE_TUNING 0x0040 +#define SDCTRL_2_SAMPLING_CLK_SEL 0x0080 +#define SDCTRL_2_ASYNC_INT_EN 0x4000 +#define SDCTRL_2_PRESET_VAL_EN 0x8000 #define SDHCI_CAPABILITIES 0x40 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F @@ -164,6 +179,7 @@ #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 #define SDHCI_CAPABILITIES_1 0x44