@@ -29,6 +29,13 @@
#define DRIVER_NAME "sdhci-pxa"
+#define SD_CLOCK_AND_BURST_SIZE_SETUP 0x10A
+#define SDCLK_DELAY_MASK 0x1F
+#define SDCLK_SEL_MASK 0x1
+#define SDCLK_DELAY_SHIFT 9
+#define SDCLK_SEL_SHIFT 8
+
+
struct sdhci_pxa {
struct sdhci_host *host;
struct sdhci_pxa_platdata *pdata;
@@ -53,7 +60,42 @@ static void enable_clock(struct sdhci_host *host)
}
}
+static void set_clock_and_burst_size(struct sdhci_host *host)
+{
+ u16 tmp;
+ struct sdhci_pxa *pxa = sdhci_priv(host);
+
+ pr_debug("%s:%s: adjust = %d\n",
+ __func__, mmc_hostname(host->mmc), pxa->pdata->adjust_clocks);
+
+ if (pxa->pdata->adjust_clocks) {
+ tmp = readw(host->ioaddr + SD_CLOCK_AND_BURST_SIZE_SETUP);
+ pr_debug("%s:%s: (B) SD_CLOCK_AND_BURST = %04X, "
+ "delay = %d, sel = %d\n",
+ __func__, mmc_hostname(host->mmc), tmp,
+ pxa->pdata->clk_delay, pxa->pdata->clk_select);
+ tmp &= ~(SDCLK_DELAY_MASK << SDCLK_DELAY_SHIFT);
+ tmp &= ~(SDCLK_SEL_MASK << SDCLK_SEL_SHIFT);
+ tmp |= (pxa->pdata->clk_delay & SDCLK_DELAY_MASK) <<
+ SDCLK_DELAY_SHIFT;
+ tmp |= (pxa->pdata->clk_select & SDCLK_SEL_MASK) <<
+ SDCLK_SEL_SHIFT;
+ writew(tmp, host->ioaddr + SD_CLOCK_AND_BURST_SIZE_SETUP);
+ pr_debug("%s:%s: (A) SD_CLOCK_AND_BURST_SIZE_SETUP = %04X\n",
+ __func__, mmc_hostname(host->mmc), tmp);
+ }
+}
+
+static void platform_reset_exit(struct sdhci_host *host, u8 mask)
+{
+ if (mask == SDHCI_RESET_ALL) {
+ /* reset private registers */
+ set_clock_and_burst_size(host);
+ }
+}
+
static struct sdhci_ops sdhci_pxa_ops = {
+ .platform_reset_exit = platform_reset_exit,
};
/*****************************************************************************\