From patchwork Tue Dec 17 02:37:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Tobias X-Patchwork-Id: 3358491 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DB135C0D4A for ; Tue, 17 Dec 2013 02:38:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1699C202EA for ; Tue, 17 Dec 2013 02:38:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4138E202E9 for ; Tue, 17 Dec 2013 02:38:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752841Ab3LQChS (ORCPT ); Mon, 16 Dec 2013 21:37:18 -0500 Received: from mail-ob0-f181.google.com ([209.85.214.181]:45976 "EHLO mail-ob0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752510Ab3LQChP (ORCPT ); Mon, 16 Dec 2013 21:37:15 -0500 Received: by mail-ob0-f181.google.com with SMTP id uy5so5602662obc.26 for ; Mon, 16 Dec 2013 18:37:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type; bh=TaSKLuwWtFdfFc2jweSmja5of2EBFSoUqof+gCKPmik=; b=rBeUFVoB/ueQJwt0gGShYX3oXP97kf73l/XUIwg9kaY7r4M3/HOPApu9LfwcYlLg7Y E7M5xp3BP5MoDAUuh2cM11dvGTcQfYf4v4aHCdtHqbC3TjzpRkCzEDcGs1+w1tsQVxiY ZAgAFOYYKWmb7/VCFFH4zBVENfq+oGJ115FsTIr0+ixhYvR5n72A+qHOJAhmIM0s0VIY pBq1KDZoNKx4+FHKx/p+vHCPxCxbfA1YPWGZFLP3WenE6Up6V06E6a0xmwuDrqsygjD+ kZWc7//Wj+an+1vtuXnYL51avvgET3PWMYG32kMfLxby8YpNAuJn4sfIIL1P9m0xa0ED 1lig== MIME-Version: 1.0 X-Received: by 10.182.204.41 with SMTP id kv9mr147166obc.78.1387247834848; Mon, 16 Dec 2013 18:37:14 -0800 (PST) Received: by 10.60.36.166 with HTTP; Mon, 16 Dec 2013 18:37:14 -0800 (PST) In-Reply-To: References: Date: Mon, 16 Dec 2013 18:37:14 -0800 Message-ID: Subject: Re: [PATCH 1/3]: Support cpu frequency scaling and power management for iMX6SL From: John Tobias To: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, Shawn Guo , Fabio Estevam , Chris Ball Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Need some correction: From: John Tobias }; On Mon, Dec 16, 2013 at 5:40 PM, John Tobias wrote: > iMX6SL device tree doesn't have a configuration settings to enable the > frequency scaling and power management. > > From: John Tobias > > > diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi > index 28558f1..0ad2f6a 100644 > --- a/arch/arm/boot/dts/imx6sl.dtsi > +++ b/arch/arm/boot/dts/imx6sl.dtsi > @@ -38,6 +38,19 @@ > device_type = "cpu"; > reg = <0x0>; > next-level-cache = <&L2>; > + operating-points = < > + /* kHz uV */ > + 1000000 1275000 > + 792000 1150000 > + >; > + clock-latency = <61036>; /* two CLK32 periods */ > + clocks = <&clks IMX6SL_CLK_ARM>, <&clks > IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, > + <&clks IMX6SL_CLK_PLL1_SW>, <&clks > IMX6SL_CLK_PLL1_SYS>; > + clock-names = "arm", "pll2_pfd2_396m", "step", > + "pll1_sw", "pll1_sys"; > + arm-supply = <®_arm>; > + pu-supply = <®_pu>; > + soc-supply = <®_soc>; > }; > }; --- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 28558f1..6035e7e 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -38,6 +38,21 @@ device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1000000 1275000 + 996000 1250000 + 792000 1150000 + 396000 950000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PLL1_SYS>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; };