From patchwork Tue Nov 9 06:28:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Jennifer Li (TP)" X-Patchwork-Id: 310242 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oA96SFQW032593 for ; Tue, 9 Nov 2010 06:28:15 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751877Ab0KIG2O (ORCPT ); Tue, 9 Nov 2010 01:28:14 -0500 Received: from sg-mxserver.o2micro.com ([203.126.184.123]:18428 "EHLO sg-mxserver-01.nt-fsrvr.o2micro.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751273Ab0KIG2O (ORCPT ); Tue, 9 Nov 2010 01:28:14 -0500 Received: from HC-EXCHANGE.nt-fsrvr.o2micro.com ([10.4.0.77]) by sg-mxserver-01.nt-fsrvr.o2micro.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 9 Nov 2010 14:28:08 +0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Subject: [PATCH 2.6.35]: Add new device IDs and registers for MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) cards. Date: Tue, 9 Nov 2010 14:28:00 +0800 Message-ID: X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Thread-Topic: [PATCH 2.6.35]: Add new device IDs and registers for MULTIMEDIA CARD (MMC), SECURE DIGITAL (SD) cards. Thread-Index: Act7/oMmwBD4WNw2SKiB1G0UMTEgKAD1zusg From: "Jennifer Li (TP)" To: Cc: "Shirley Her (SC)" , "Hardys Lv(WH)" , "Rich Lin (TP)" , "Samuel Guan(WH)" , , , , "Chris Van Hoof" X-OriginalArrivalTime: 09 Nov 2010 06:28:08.0556 (UTC) FILETIME=[465FA2C0:01CB7FD7] Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Tue, 09 Nov 2010 06:28:15 +0000 (UTC) --- /home/j/Desktop/kernel_source_1104/linux-2.6.35/drivers/mmc/host/sdhci-pci.c    2010-08-02 06:11:14.000000000 +0800 +++ /home/j/Desktop/SD_ADMAissue_8220_8320/20101020_sdhci_pci_c/sdhci-pci.c 2010-10-20 23:44:50.000000000 +0800 @@ -39,6 +39,26 @@    #define MAX_SLOTS          8   +#ifndef PCI_DEVICE_ID_O2_8120 +#define PCI_DEVICE_ID_O2_8120      0x8120 +#endif + +#ifndef PCI_DEVICE_ID_O2_8220 +#define PCI_DEVICE_ID_O2_8220      0x8220 +#endif + +#ifndef PCI_DEVICE_ID_O2_8320 +#define PCI_DEVICE_ID_O2_8320      0x8320 +#endif + +#ifndef PCI_DEVICE_ID_O2_8321 +#define PCI_DEVICE_ID_O2_8321      0x8321 +#endif + +#ifndef PCI_DEVICE_ID_O2_8221 +#define PCI_DEVICE_ID_O2_8221      0x8221 +#endif +  struct sdhci_pci_chip;  struct sdhci_pci_slot;   @@ -112,6 +132,118 @@ static const struct sdhci_pci_fixes sdhc               SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,  };   +static int o2_probe(struct sdhci_pci_chip *chip) +{ +   int ret; +   u8 scratch; + +   if ((chip->pdev->device == PCI_DEVICE_ID_O2_8220) || +       (chip->pdev->device == PCI_DEVICE_ID_O2_8320) || +       (chip->pdev->device == PCI_DEVICE_ID_O2_8321) || +       (chip->pdev->device == PCI_DEVICE_ID_O2_8221)) +       { +       //set D3 to 0x7f +       ret = pci_read_config_byte(chip->pdev, 0xD3, &scratch); +       if (ret) +           return ret; +   +       scratch &= 0x7f;    + +       ret = pci_write_config_byte(chip->pdev, 0xD3, scratch); +       if (ret) +           return ret; + +       // set EE to 08 +       ret = pci_read_config_byte(chip->pdev, 0xEE, &scratch); +       if (ret) +           return ret; +   +       scratch = 0x08; + +       ret = pci_write_config_byte(chip->pdev, 0xEE, scratch); +       if (ret) +           return ret; + +       // set Ec to 0x20 +       ret = pci_read_config_byte(chip->pdev, 0xEC, &scratch); +       if (ret) +           return ret; +   +       scratch |= 0x20;    + +       ret = pci_write_config_byte(chip->pdev, 0xEC, scratch); +       if (ret) +           return ret; + +       // set E0 to 0x01 +       ret = pci_read_config_byte(chip->pdev, 0xE0, &scratch); +       if (ret) +           return ret; +   +       scratch |= 0x01;    + +       ret = pci_write_config_byte(chip->pdev, 0xE0, scratch); +       if (ret) +           return ret; + +       // set E0 to 0x73 +       ret = pci_read_config_byte(chip->pdev, 0xE0, &scratch); +       if (ret) +           return ret; +   +       scratch = 0x73; + +       ret = pci_write_config_byte(chip->pdev, 0xE0, scratch); +       if (ret) +           return ret; + +       // set E2 to 0x39 +       ret = pci_read_config_byte(chip->pdev, 0xE2, &scratch); +       if (ret) +           return ret; +   +       scratch = 0x39; + +       ret = pci_write_config_byte(chip->pdev, 0xE2, scratch); +       if (ret) +           return ret; + +       // set E7 to 0x08 +       ret = pci_read_config_byte(chip->pdev, 0xE7, &scratch); +       if (ret) +           return ret; +   +       scratch = 0x08; + +       ret = pci_write_config_byte(chip->pdev, 0xE7, scratch); +       if (ret) +           return ret; + +       // set f1 to 0x08 +       ret = pci_read_config_byte(chip->pdev, 0xF1, &scratch); +       if (ret) +           return ret; +   +       scratch |= 0x08;    + +       ret = pci_write_config_byte(chip->pdev, 0xF1, scratch); +       if (ret) +           return ret; + +       //set D3 to 80 +       ret = pci_read_config_byte(chip->pdev, 0xD3, &scratch); +       if (ret) +           return ret; + +       scratch |= 0x80;    +   +       ret = pci_write_config_byte(chip->pdev, 0xD3, scratch); +       if (ret) +           return ret; +       } +   return 0; +} +  static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)  {     u8 scratch; @@ -275,6 +407,11 @@ static int jmicron_resume(struct sdhci_p     return 0;  }   +static const struct sdhci_pci_fixes sdhci_o2 = { +   .probe      = o2_probe, +// .quirks     = SDHCI_QUICK_ADMA_TABLE_ENTRY, +}; +  static const struct sdhci_pci_fixes sdhci_jmicron = {     .probe      = jmicron_probe,   @@ -445,6 +582,46 @@ static const struct pci_device_id pci_id         .driver_data    = (kernel_ulong_t)&sdhci_via,     },   +   { +       .vendor     = PCI_VENDOR_ID_O2, +       .device     = PCI_DEVICE_ID_O2_8120, +       .subvendor  = PCI_ANY_ID, +       .subdevice  = PCI_ANY_ID, +       .driver_data    = (kernel_ulong_t)&sdhci_o2, +   }, + +   { +       .vendor     = PCI_VENDOR_ID_O2, +       .device     = PCI_DEVICE_ID_O2_8220, +       .subvendor  = PCI_ANY_ID, +       .subdevice  = PCI_ANY_ID, +       .driver_data    = (kernel_ulong_t)&sdhci_o2, +   }, + +   { +       .vendor     = PCI_VENDOR_ID_O2, +       .device     = PCI_DEVICE_ID_O2_8320, +       .subvendor  = PCI_ANY_ID, +       .subdevice  = PCI_ANY_ID, +       .driver_data    = (kernel_ulong_t)&sdhci_o2, +   }, + +   { +       .vendor     = PCI_VENDOR_ID_O2, +       .device     = PCI_DEVICE_ID_O2_8221, +       .subvendor  = PCI_ANY_ID, +       .subdevice  = PCI_ANY_ID, +       .driver_data    = (kernel_ulong_t)&sdhci_o2, +   }, + +   { +       .vendor     = PCI_VENDOR_ID_O2, +       .device     = PCI_DEVICE_ID_O2_8321, +       .subvendor  = PCI_ANY_ID, +       .subdevice  = PCI_ANY_ID, +       .driver_data    = (kernel_ulong_t)&sdhci_o2, +   }, +     {   /* Generic SD host controller */         PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)     },