From patchwork Tue Dec 25 02:43:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: wei_wang@realsil.com.cn X-Patchwork-Id: 1909271 Return-Path: X-Original-To: patchwork-linux-mmc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 1D8AD3FC66 for ; Tue, 25 Dec 2012 02:44:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753638Ab2LYCoL (ORCPT ); Mon, 24 Dec 2012 21:44:11 -0500 Received: from rtits2.realtek.com ([60.250.210.242]:35005 "EHLO rtits2.realtek.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753622Ab2LYCoH (ORCPT ); Mon, 24 Dec 2012 21:44:07 -0500 X-SpamFilter-By: BOX Solutions SpamTrap 5.19 with qID qBP2hZ9L021298, This message is released by code: ctaloc0852 Received: from RSEX1.realsil.com.cn (rsl1.realsil.com.cn [172.29.17.2] (may be forged)) by rtits2.realtek.com (8.14.5/2.19/5.24) with ESMTP id qBP2hZ9L021298; Tue, 25 Dec 2012 10:43:35 +0800 Received: from localhost (172.29.41.8) by RSEX1.realsil.com.cn (172.29.17.2) with Microsoft SMTP Server id 8.3.213.0; Tue, 25 Dec 2012 10:43:36 +0800 From: To: , CC: , , , , , , , Wei WANG Subject: [PATCH v2 7/8] MFD:rtsx: Fix checkpatch warning Date: Tue, 25 Dec 2012 10:43:34 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Wei WANG WARNING: Avoid CamelCase: + u8 N, min_N, max_N, clk_divider; WARNING: Avoid CamelCase: + u8 N, min_N, max_N, clk_divider; Signed-off-by: Wei WANG --- drivers/mfd/rtsx_pcr.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/mfd/rtsx_pcr.c b/drivers/mfd/rtsx_pcr.c index 958b738..7632e7f 100644 --- a/drivers/mfd/rtsx_pcr.c +++ b/drivers/mfd/rtsx_pcr.c @@ -590,7 +590,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) { int err, clk; - u8 N, min_N, max_N, clk_divider; + u8 n, min_n, max_n, clk_divider; u8 mcu_cnt, div, max_div; u8 depth[] = { [RTSX_SSC_DEPTH_4M] = SSC_DEPTH_4M, @@ -615,8 +615,8 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, card_clock /= 1000000; dev_dbg(&(pcr->pci->dev), "Switch card clock to %dMHz\n", card_clock); - min_N = 80; - max_N = 208; + min_n = 80; + max_n = 208; max_div = CLK_DIV_8; clk = card_clock; @@ -630,30 +630,30 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, return 0; if (pcr->ops->conv_clk_and_div_n) - N = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); + n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); else - N = (u8)(clk - 2); - if ((clk <= 2) || (N > max_N)) + n = (u8)(clk - 2); + if ((clk <= 2) || (n > max_n)) return -EINVAL; mcu_cnt = (u8)(125/clk + 3); if (mcu_cnt > 15) mcu_cnt = 15; - /* Make sure that the SSC clock div_n is equal or greater than min_N */ + /* Make sure that the SSC clock div_n is equal or greater than min_n */ div = CLK_DIV_1; - while ((N < min_N) && (div < max_div)) { + while ((n < min_n) && (div < max_div)) { if (pcr->ops->conv_clk_and_div_n) { - int dbl_clk = pcr->ops->conv_clk_and_div_n(N, + int dbl_clk = pcr->ops->conv_clk_and_div_n(n, DIV_N_TO_CLK) * 2; - N = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, + n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk, CLK_TO_DIV_N); } else { - N = (N + 2) * 2 - 2; + n = (n + 2) * 2 - 2; } div++; } - dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", N, div); + dev_dbg(&(pcr->pci->dev), "N = %d, div = %d\n", n, div); ssc_depth = depth[ssc_depth]; if (double_clk) @@ -670,7 +670,7 @@ int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK, ssc_depth); - rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); + rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); if (vpclk) { rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,