[RFC,V3,09/43] rv64ilp32_abi: riscv: Reuse LP64 SBI interface

Commit Message

Guo Ren March 25, 2025, 12:15 p.m. UTC

From: "Guo Ren (Alibaba DAMO Academy)" <[e-mail]>

The RV64ILP32 ABI leverages the LP64 SBI interface, enabling the
RV64ILP32 Linux kernel to run seamlessly on LP64 OpenSBI or KVM.
Using RV64ILP32 Linux doesn't require changing the bootloader,
firmware, or hypervisor; it could replace the LP64 kernel directly.

Signed-off-by: Guo Ren (Alibaba DAMO Academy) <[e-mail]>
---
 arch/riscv/include/asm/cpu_ops_sbi.h |  4 ++--
 arch/riscv/include/asm/sbi.h         | 22 +++++++++++-----------
 arch/riscv/kernel/cpu_ops_sbi.c      |  4 ++--
 arch/riscv/kernel/sbi_ecall.c        | 22 +++++++++++-----------
 4 files changed, 26 insertions(+), 26 deletions(-)

Patch

diff --git a/arch/riscv/include/asm/cpu_ops_sbi.h b/arch/riscv/include/asm/cpu_ops_sbi.h
index d6e4665b3195..d967adad6b48 100644
--- a/arch/riscv/include/asm/cpu_ops_sbi.h
+++ b/arch/riscv/include/asm/cpu_ops_sbi.h
@@ -19,8 +19,8 @@  extern const struct cpu_operations cpu_ops_sbi;
  * @stack_ptr: A pointer to the hart specific sp
  */
 struct sbi_hart_boot_data {
-	void *task_ptr;
-	void *stack_ptr;
+	xlen_t task_ptr;
+	xlen_t stack_ptr;
 };
 #endif
 
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index 3d250824178b..fd9a9c723ec6 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -138,16 +138,16 @@  enum sbi_ext_pmu_fid {
 };
 
 union sbi_pmu_ctr_info {
-	unsigned long value;
+	xlen_t value;
 	struct {
-		unsigned long csr:12;
-		unsigned long width:6;
+		xlen_t csr:12;
+		xlen_t width:6;
 #if __riscv_xlen == 32
-		unsigned long reserved:13;
+		xlen_t reserved:13;
 #else
-		unsigned long reserved:45;
+		xlen_t reserved:45;
 #endif
-		unsigned long type:1;
+		xlen_t type:1;
 	};
 };
 
@@ -422,15 +422,15 @@  enum sbi_ext_nacl_feature {
 
 extern unsigned long sbi_spec_version;
 struct sbiret {
-	long error;
-	long value;
+	xlen_t error;
+	xlen_t value;
 };
 
 void sbi_init(void);
 long __sbi_base_ecall(int fid);
-struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
-			  unsigned long arg2, unsigned long arg3,
-			  unsigned long arg4, unsigned long arg5,
+struct sbiret __sbi_ecall(xlen_t arg0, xlen_t arg1,
+			  xlen_t arg2, xlen_t arg3,
+			  xlen_t arg4, xlen_t arg5,
 			  int fid, int ext);
 #define sbi_ecall(e, f, a0, a1, a2, a3, a4, a5)	\
 		__sbi_ecall(a0, a1, a2, a3, a4, a5, f, e)
diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c
index e6fbaaf54956..f9ef3c0155f4 100644
--- a/arch/riscv/kernel/cpu_ops_sbi.c
+++ b/arch/riscv/kernel/cpu_ops_sbi.c
@@ -71,8 +71,8 @@  static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle)
 
 	/* Make sure tidle is updated */
 	smp_mb();
-	bdata->task_ptr = tidle;
-	bdata->stack_ptr = task_pt_regs(tidle);
+	bdata->task_ptr = (ulong)tidle;
+	bdata->stack_ptr = (ulong)task_pt_regs(tidle);
 	/* Make sure boot data is updated */
 	smp_mb();
 	hsm_data = __pa(bdata);
diff --git a/arch/riscv/kernel/sbi_ecall.c b/arch/riscv/kernel/sbi_ecall.c
index 24aabb4fbde3..ee22e69d70da 100644
--- a/arch/riscv/kernel/sbi_ecall.c
+++ b/arch/riscv/kernel/sbi_ecall.c
@@ -17,23 +17,23 @@  long __sbi_base_ecall(int fid)
 }
 EXPORT_SYMBOL(__sbi_base_ecall);
 
-struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
-			  unsigned long arg2, unsigned long arg3,
-			  unsigned long arg4, unsigned long arg5,
+struct sbiret __sbi_ecall(xlen_t arg0, xlen_t arg1,
+			  xlen_t arg2, xlen_t arg3,
+			  xlen_t arg4, xlen_t arg5,
 			  int fid, int ext)
 {
 	struct sbiret ret;
 
 	trace_sbi_call(ext, fid);
 
-	register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
-	register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
-	register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
-	register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
-	register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
-	register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
-	register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
-	register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
+	register xlen_t a0 asm ("a0") = (xlen_t)(arg0);
+	register xlen_t a1 asm ("a1") = (xlen_t)(arg1);
+	register xlen_t a2 asm ("a2") = (xlen_t)(arg2);
+	register xlen_t a3 asm ("a3") = (xlen_t)(arg3);
+	register xlen_t a4 asm ("a4") = (xlen_t)(arg4);
+	register xlen_t a5 asm ("a5") = (xlen_t)(arg5);
+	register xlen_t a6 asm ("a6") = (xlen_t)(fid);
+	register xlen_t a7 asm ("a7") = (xlen_t)(ext);
 	asm volatile ("ecall"
 		       : "+r" (a0), "+r" (a1)
 		       : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)