Message ID | 20200701072235.223558-1-aneesh.kumar@linux.ibm.com (mailing list archive) |
---|---|
Headers | show |
Series | Support new pmem flush and sync instructions for POWER | expand |
On Wed, 1 Jul 2020 12:52:28 +0530, Aneesh Kumar K.V wrote: > This patch series enables the usage os new pmem flush and sync instructions on POWER > architecture. POWER10 introduces two new variants of dcbf instructions (dcbstps and dcbfps) > that can be used to write modified locations back to persistent storage. Additionally, > POWER10 also introduce phwsync and plwsync which can be used to establish order of these > writes to persistent storage. > > This series exposes these instructions to the rest of the kernel. The existing > dcbf and hwsync instructions in P8 and P9 are adequate to enable appropriate > synchronization with OpenCAPI-hosted persistent storage. Hence the new instructions > are added as a variant of the old ones that old hardware won't differentiate. > > [...] Applied to powerpc/next. [1/7] powerpc/pmem: Restrict papr_scm to P8 and above. https://git.kernel.org/powerpc/c/c83040192f3763b243ece26073d61a895b4a230f [2/7] powerpc/pmem: Add new instructions for persistent storage and sync https://git.kernel.org/powerpc/c/32db09d992ddc7d145595cff49cccfe14e018266 [3/7] powerpc/pmem: Add flush routines using new pmem store and sync instruction https://git.kernel.org/powerpc/c/d358042793183a57094dac45a44116e1165ac593 [4/7] libnvdimm/nvdimm/flush: Allow architecture to override the flush barrier https://git.kernel.org/powerpc/c/3e79f082ebfc130360bcee23e4dd74729dcafdf4 [5/7] powerpc/pmem: Update ppc64 to use the new barrier instruction. https://git.kernel.org/powerpc/c/76e6c73f33d4e1cc4de4f25c0bf66d59e42113c4 [6/7] powerpc/pmem: Avoid the barrier in flush routines https://git.kernel.org/powerpc/c/436499ab868f1a9e497cfdbf641affe8a122c571 [7/7] powerpc/pmem: Initialize pmem device on newer hardware https://git.kernel.org/powerpc/c/8c26ab72663b4affc31e47cdf77d61d0172d1033 cheers