| Message ID | 165603886721.551046.8682583835505795210.stgit@dwillia2-xfh (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | CXL PMEM Region Provisioning | expand |
On Thu, 23 Jun 2022 19:47:47 -0700 Dan Williams <dan.j.williams@intel.com> wrote: > For the x2 host-bridge interleave windows, allow for a > x8-endpoint-interleave configuration per memory-type with each device > contributing the minimum 256MB extent. Similarly, for the x1 host-bridge > interleave windows, allow for a x4-endpoint-interleave configuration per > memory-type. > > Bump up the number of decoders per-port to support hosting 8 regions. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Hmm. I should get around to adding multiple decoders to the programmable bits of the QEMU emulation to give us more flexibility. Mind you volatile memory support would probably also be good ;) Jonathan > --- > tools/testing/cxl/test/cxl.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c > index b6e6bc02a507..599326796b83 100644 > --- a/tools/testing/cxl/test/cxl.c > +++ b/tools/testing/cxl/test/cxl.c > @@ -14,7 +14,7 @@ > #define NR_CXL_HOST_BRIDGES 2 > #define NR_CXL_ROOT_PORTS 2 > #define NR_CXL_SWITCH_PORTS 2 > -#define NR_CXL_PORT_DECODERS 2 > +#define NR_CXL_PORT_DECODERS 8 > > static struct platform_device *cxl_acpi; > static struct platform_device *cxl_host_bridge[NR_CXL_HOST_BRIDGES]; > @@ -118,7 +118,7 @@ static struct { > .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | > ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, > .qtg_id = 0, > - .window_size = SZ_256M, > + .window_size = SZ_256M * 4UL, > }, > .target = { 0 }, > }, > @@ -133,7 +133,7 @@ static struct { > .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | > ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, > .qtg_id = 1, > - .window_size = SZ_256M * 2, > + .window_size = SZ_256M * 8UL, > }, > .target = { 0, 1, }, > }, > @@ -148,7 +148,7 @@ static struct { > .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | > ACPI_CEDT_CFMWS_RESTRICT_PMEM, > .qtg_id = 2, > - .window_size = SZ_256M, > + .window_size = SZ_256M * 4UL, > }, > .target = { 0 }, > }, > @@ -163,7 +163,7 @@ static struct { > .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | > ACPI_CEDT_CFMWS_RESTRICT_PMEM, > .qtg_id = 3, > - .window_size = SZ_256M * 2, > + .window_size = SZ_256M * 8UL, > }, > .target = { 0, 1, }, > }, >
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index b6e6bc02a507..599326796b83 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -14,7 +14,7 @@ #define NR_CXL_HOST_BRIDGES 2 #define NR_CXL_ROOT_PORTS 2 #define NR_CXL_SWITCH_PORTS 2 -#define NR_CXL_PORT_DECODERS 2 +#define NR_CXL_PORT_DECODERS 8 static struct platform_device *cxl_acpi; static struct platform_device *cxl_host_bridge[NR_CXL_HOST_BRIDGES]; @@ -118,7 +118,7 @@ static struct { .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, .qtg_id = 0, - .window_size = SZ_256M, + .window_size = SZ_256M * 4UL, }, .target = { 0 }, }, @@ -133,7 +133,7 @@ static struct { .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | ACPI_CEDT_CFMWS_RESTRICT_VOLATILE, .qtg_id = 1, - .window_size = SZ_256M * 2, + .window_size = SZ_256M * 8UL, }, .target = { 0, 1, }, }, @@ -148,7 +148,7 @@ static struct { .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id = 2, - .window_size = SZ_256M, + .window_size = SZ_256M * 4UL, }, .target = { 0 }, }, @@ -163,7 +163,7 @@ static struct { .restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 | ACPI_CEDT_CFMWS_RESTRICT_PMEM, .qtg_id = 3, - .window_size = SZ_256M * 2, + .window_size = SZ_256M * 8UL, }, .target = { 0, 1, }, },
For the x2 host-bridge interleave windows, allow for a x8-endpoint-interleave configuration per memory-type with each device contributing the minimum 256MB extent. Similarly, for the x1 host-bridge interleave windows, allow for a x4-endpoint-interleave configuration per memory-type. Bump up the number of decoders per-port to support hosting 8 regions. Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- tools/testing/cxl/test/cxl.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)