From patchwork Tue Jun 5 20:58:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ross Zwisler X-Patchwork-Id: 10449209 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 12F1B60467 for ; Tue, 5 Jun 2018 20:59:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 033F129C51 for ; Tue, 5 Jun 2018 20:59:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EC50129C59; Tue, 5 Jun 2018 20:59:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from ml01.01.org (ml01.01.org [198.145.21.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 55F5429C51 for ; Tue, 5 Jun 2018 20:59:03 +0000 (UTC) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 019B5211C6488; Tue, 5 Jun 2018 13:59:03 -0700 (PDT) X-Original-To: linux-nvdimm@lists.01.org Delivered-To: linux-nvdimm@lists.01.org Received-SPF: None (no SPF record) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=ross.zwisler@linux.intel.com; receiver=linux-nvdimm@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1377211EFEE3 for ; Tue, 5 Jun 2018 13:59:01 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Jun 2018 13:59:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,479,1520924400"; d="scan'208";a="234933763" Received: from theros.lm.intel.com ([10.232.112.164]) by fmsmga006.fm.intel.com with ESMTP; 05 Jun 2018 13:59:01 -0700 From: Ross Zwisler To: linux-kernel@vger.kernel.org Subject: [PATCH 2/2] libnvdimm: don't flush power-fail protected CPU caches Date: Tue, 5 Jun 2018 14:58:41 -0600 Message-Id: <20180605205841.15878-2-ross.zwisler@linux.intel.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180605205841.15878-1-ross.zwisler@linux.intel.com> References: <20180605205841.15878-1-ross.zwisler@linux.intel.com> X-BeenThere: linux-nvdimm@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: "Linux-nvdimm developer list." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-nvdimm@lists.01.org MIME-Version: 1.0 Errors-To: linux-nvdimm-bounces@lists.01.org Sender: "Linux-nvdimm" X-Virus-Scanned: ClamAV using ClamSMTP This commit: 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()") intended to make sure that deep flush was always available even on platforms which support a power-fail protected CPU cache. An unintended side effect of this change was that we also lost the ability to skip flushing CPU caches on those power-fail protected CPU cache. Signed-off-by: Ross Zwisler Fixes: 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()") --- drivers/dax/super.c | 20 +++++++++++++++++++- drivers/nvdimm/pmem.c | 2 ++ include/linux/dax.h | 9 +++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/dax/super.c b/drivers/dax/super.c index c2c46f96b18c..457e0bb6c936 100644 --- a/drivers/dax/super.c +++ b/drivers/dax/super.c @@ -152,6 +152,8 @@ enum dax_device_flags { DAXDEV_ALIVE, /* gate whether dax_flush() calls the low level flush routine */ DAXDEV_WRITE_CACHE, + /* only flush the CPU caches if they are not power fail protected */ + DAXDEV_FLUSH_ON_SYNC, }; /** @@ -283,7 +285,8 @@ EXPORT_SYMBOL_GPL(dax_copy_from_iter); void arch_wb_cache_pmem(void *addr, size_t size); void dax_flush(struct dax_device *dax_dev, void *addr, size_t size) { - if (unlikely(!dax_write_cache_enabled(dax_dev))) + if (unlikely(!dax_write_cache_enabled(dax_dev)) || + !dax_flush_on_sync_enabled(dax_dev)) return; arch_wb_cache_pmem(addr, size); @@ -310,6 +313,21 @@ bool dax_write_cache_enabled(struct dax_device *dax_dev) } EXPORT_SYMBOL_GPL(dax_write_cache_enabled); +void dax_flush_on_sync(struct dax_device *dax_dev, bool flush) +{ + if (flush) + set_bit(DAXDEV_FLUSH_ON_SYNC, &dax_dev->flags); + else + clear_bit(DAXDEV_FLUSH_ON_SYNC, &dax_dev->flags); +} +EXPORT_SYMBOL_GPL(dax_flush_on_sync); + +bool dax_flush_on_sync_enabled(struct dax_device *dax_dev) +{ + return test_bit(DAXDEV_FLUSH_ON_SYNC, &dax_dev->flags); +} +EXPORT_SYMBOL_GPL(dax_flush_on_sync_enabled); + bool dax_alive(struct dax_device *dax_dev) { lockdep_assert_held(&dax_srcu); diff --git a/drivers/nvdimm/pmem.c b/drivers/nvdimm/pmem.c index 9d714926ecf5..faeb2deae7f0 100644 --- a/drivers/nvdimm/pmem.c +++ b/drivers/nvdimm/pmem.c @@ -414,6 +414,8 @@ static int pmem_attach_disk(struct device *dev, return -ENOMEM; } dax_write_cache(dax_dev, wbc); + dax_flush_on_sync(dax_dev, + !test_bit(ND_REGION_PERSIST_CACHE, &nd_region->flags)); pmem->dax_dev = dax_dev; gendev = disk_to_dev(disk); diff --git a/include/linux/dax.h b/include/linux/dax.h index f9eb22ad341e..1e6086405a1a 100644 --- a/include/linux/dax.h +++ b/include/linux/dax.h @@ -32,6 +32,8 @@ void put_dax(struct dax_device *dax_dev); void kill_dax(struct dax_device *dax_dev); void dax_write_cache(struct dax_device *dax_dev, bool wc); bool dax_write_cache_enabled(struct dax_device *dax_dev); +void dax_flush_on_sync(struct dax_device *dax_dev, bool flush); +bool dax_flush_on_sync_enabled(struct dax_device *dax_dev); #else static inline struct dax_device *dax_get_by_host(const char *host) { @@ -59,6 +61,13 @@ static inline bool dax_write_cache_enabled(struct dax_device *dax_dev) { return false; } +static inline void dax_flush_on_sync(struct dax_device *dax_dev, bool flush) +{ +} +static inline bool dax_flush_on_sync_enabled(struct dax_device *dax_dev) +{ + return false; +} #endif struct writeback_control;