From patchwork Fri Feb 21 03:27:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alastair D'Silva X-Patchwork-Id: 11395407 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 086FE1580 for ; Fri, 21 Feb 2020 03:28:58 +0000 (UTC) Received: from ml01.01.org (ml01.01.org [198.145.21.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4F5A20716 for ; Fri, 21 Feb 2020 03:28:57 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E4F5A20716 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=au1.ibm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-nvdimm-bounces@lists.01.org Received: from ml01.vlan13.01.org (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id A9F9C10FC3633; Thu, 20 Feb 2020 19:29:25 -0800 (PST) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=alastair@au1.ibm.com; receiver= Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 304A910FC3632 for ; Thu, 20 Feb 2020 19:29:20 -0800 (PST) Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01L3JK9K021308 for ; Thu, 20 Feb 2020 22:28:27 -0500 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2y8ucnrcg4-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 20 Feb 2020 22:28:27 -0500 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 21 Feb 2020 03:28:11 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 01L3SAF852232288 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 21 Feb 2020 03:28:10 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B1D98A405B; Fri, 21 Feb 2020 03:28:10 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 16A03A405C; Fri, 21 Feb 2020 03:28:10 +0000 (GMT) Received: from ozlabs.au.ibm.com (unknown [9.192.253.14]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 21 Feb 2020 03:28:10 +0000 (GMT) Received: from adsilva.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.au.ibm.com (Postfix) with ESMTPSA id ACDD4A03E0; Fri, 21 Feb 2020 14:28:03 +1100 (AEDT) From: "Alastair D'Silva" To: alastair@d-silva.org Subject: [PATCH v3 19/27] powerpc/powernv/pmem: Add an IOCTL to report controller statistics Date: Fri, 21 Feb 2020 14:27:12 +1100 X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200221032720.33893-1-alastair@au1.ibm.com> References: <20200221032720.33893-1-alastair@au1.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20022103-0012-0000-0000-00000388D1D2 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20022103-0013-0000-0000-000021C56A71 Message-Id: <20200221032720.33893-20-alastair@au1.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138,18.0.572 definitions=2020-02-20_19:2020-02-19,2020-02-20 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 mlxlogscore=622 priorityscore=1501 clxscore=1015 suspectscore=1 bulkscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2001150001 definitions=main-2002210020 Message-ID-Hash: VXGS2IIY5PAIG7SM3HSMPDJW6BQK5YPR X-Message-ID-Hash: VXGS2IIY5PAIG7SM3HSMPDJW6BQK5YPR X-MailFrom: alastair@au1.ibm.com X-Mailman-Rule-Hits: nonmember-moderation X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation CC: "Aneesh Kumar K . V" , Benjamin Herrenschmidt , Paul Mackerras , Michael Ellerman , Frederic Barrat , Andrew Donnellan , Arnd Bergmann , Greg Kroah-Hartman , Andrew Morton , Mauro Carvalho Chehab , "David S. Miller" , Rob Herring , Anton Blanchard , Krzysztof Kozlowski , Mahesh Salgaonkar , Madhavan Srinivasan , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Anju T Sudhakar , Hari Bathini , Thomas Gleixner , Greg Kurz , Nicholas Piggin , Masahiro Yamada , Alexey Kardashevskiy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-nvdimm@lists.01.org, linux-mm@kvack.org X-Mailman-Version: 3.1.1 Precedence: list List-Id: "Linux-nvdimm developer list." Archived-At: List-Archive: List-Help: List-Post: List-Subscribe: List-Unsubscribe: From: Alastair D'Silva The controller can report a number of statistics that are useful in evaluating the performance and reliability of the card. This patch exposes this information via an IOCTL. Signed-off-by: Alastair D'Silva --- arch/powerpc/platforms/powernv/pmem/ocxl.c | 185 +++++++++++++++++++++ include/uapi/nvdimm/ocxl-pmem.h | 17 ++ 2 files changed, 202 insertions(+) diff --git a/arch/powerpc/platforms/powernv/pmem/ocxl.c b/arch/powerpc/platforms/powernv/pmem/ocxl.c index 2cabafe1fc58..009d4fd29e7d 100644 --- a/arch/powerpc/platforms/powernv/pmem/ocxl.c +++ b/arch/powerpc/platforms/powernv/pmem/ocxl.c @@ -758,6 +758,186 @@ static int ioctl_controller_dump_complete(struct ocxlpmem *ocxlpmem) GLOBAL_MMIO_HCI_CONTROLLER_DUMP_COLLECTED); } +/** + * controller_stats_header_parse() - Parse the first 64 bits of the controller stats admin command response + * @ocxlpmem: the device metadata + * @length: out, returns the number of bytes in the response (excluding the 64 bit header) + */ +static int controller_stats_header_parse(struct ocxlpmem *ocxlpmem, + u32 *length) +{ + int rc; + u64 val; + + u16 data_identifier; + u32 data_length; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset, + OCXL_LITTLE_ENDIAN, &val); + if (rc) + return rc; + + data_identifier = val >> 48; + data_length = val & 0xFFFFFFFF; + + if (data_identifier != 0x4353) { // 'CS' + dev_err(&ocxlpmem->dev, + "Bad data identifier for controller stats, expected 'CS', got '%-.*s'\n", + 2, (char *)&data_identifier); + return -EINVAL; + } + + *length = data_length; + return 0; +} + +static int ioctl_controller_stats(struct ocxlpmem *ocxlpmem, + struct ioctl_ocxl_pmem_controller_stats __user *uarg) +{ + struct ioctl_ocxl_pmem_controller_stats args; + u32 length; + int rc; + u64 val; + + memset(&args, '\0', sizeof(args)); + + mutex_lock(&ocxlpmem->admin_command.lock); + + rc = admin_command_request(ocxlpmem, ADMIN_COMMAND_CONTROLLER_STATS); + if (rc) + goto out; + + rc = ocxl_global_mmio_write64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.request_offset + 0x08, + OCXL_LITTLE_ENDIAN, 0); + if (rc) + goto out; + + rc = admin_command_execute(ocxlpmem); + if (rc) + goto out; + + + rc = admin_command_complete_timeout(ocxlpmem, + ADMIN_COMMAND_CONTROLLER_STATS); + if (rc < 0) { + dev_warn(&ocxlpmem->dev, "Controller stats timed out\n"); + goto out; + } + + rc = admin_response(ocxlpmem); + if (rc < 0) + goto out; + if (rc != STATUS_SUCCESS) { + warn_status(ocxlpmem, + "Unexpected status from controller stats", rc); + goto out; + } + + rc = controller_stats_header_parse(ocxlpmem, &length); + if (rc) + goto out; + + if (length != 0x140) + warn_status(ocxlpmem, + "Unexpected length for controller stats data, expected 0x140, got 0x%x", + length); + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x08, + OCXL_LITTLE_ENDIAN, &val); + if (rc) + goto out; + + args.reset_count = val >> 32; + args.reset_uptime = val & 0xFFFFFFFF; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x10, + OCXL_LITTLE_ENDIAN, &val); + if (rc) + goto out; + + args.power_on_uptime = val >> 32; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x08, + OCXL_LITTLE_ENDIAN, &args.host_load_count); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x10, + OCXL_LITTLE_ENDIAN, &args.host_store_count); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x18, + OCXL_LITTLE_ENDIAN, &args.media_read_count); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x20, + OCXL_LITTLE_ENDIAN, &args.media_write_count); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x28, + OCXL_LITTLE_ENDIAN, &args.cache_hit_count); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x30, + OCXL_LITTLE_ENDIAN, &args.cache_miss_count); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x38, + OCXL_LITTLE_ENDIAN, &args.media_read_latency); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x40, + OCXL_LITTLE_ENDIAN, &args.media_write_latency); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x48, + OCXL_LITTLE_ENDIAN, &args.cache_read_latency); + if (rc) + goto out; + + rc = ocxl_global_mmio_read64(ocxlpmem->ocxl_afu, + ocxlpmem->admin_command.data_offset + 0x08 + 0x40 + 0x50, + OCXL_LITTLE_ENDIAN, &args.cache_write_latency); + if (rc) + goto out; + + if (copy_to_user(uarg, &args, sizeof(args))) { + rc = -EFAULT; + goto out; + } + + rc = admin_response_handled(ocxlpmem); + if (rc) + goto out; + + rc = 0; + goto out; + +out: + mutex_unlock(&ocxlpmem->admin_command.lock); + return rc; +} + static long file_ioctl(struct file *file, unsigned int cmd, unsigned long args) { struct ocxlpmem *ocxlpmem = file->private_data; @@ -781,6 +961,11 @@ static long file_ioctl(struct file *file, unsigned int cmd, unsigned long args) case IOCTL_OCXL_PMEM_CONTROLLER_DUMP_COMPLETE: rc = ioctl_controller_dump_complete(ocxlpmem); break; + + case IOCTL_OCXL_PMEM_CONTROLLER_STATS: + rc = ioctl_controller_stats(ocxlpmem, + (struct ioctl_ocxl_pmem_controller_stats __user *)args); + break; } return rc; diff --git a/include/uapi/nvdimm/ocxl-pmem.h b/include/uapi/nvdimm/ocxl-pmem.h index d4d8512d03f7..add223aa2fdb 100644 --- a/include/uapi/nvdimm/ocxl-pmem.h +++ b/include/uapi/nvdimm/ocxl-pmem.h @@ -50,6 +50,22 @@ struct ioctl_ocxl_pmem_controller_dump_data { __u64 reserved[8]; }; +struct ioctl_ocxl_pmem_controller_stats { + __u32 reset_count; + __u32 reset_uptime; /* seconds */ + __u32 power_on_uptime; /* seconds */ + __u64 host_load_count; + __u64 host_store_count; + __u64 media_read_count; + __u64 media_write_count; + __u64 cache_hit_count; + __u64 cache_miss_count; + __u64 media_read_latency; /* nanoseconds */ + __u64 media_write_latency; /* nanoseconds */ + __u64 cache_read_latency; /* nanoseconds */ + __u64 cache_write_latency; /* nanoseconds */ +}; + /* ioctl numbers */ #define OCXL_PMEM_MAGIC 0x5C /* SCM devices */ @@ -57,5 +73,6 @@ struct ioctl_ocxl_pmem_controller_dump_data { #define IOCTL_OCXL_PMEM_CONTROLLER_DUMP _IO(OCXL_PMEM_MAGIC, 0x02) #define IOCTL_OCXL_PMEM_CONTROLLER_DUMP_DATA _IOWR(OCXL_PMEM_MAGIC, 0x03, struct ioctl_ocxl_pmem_controller_dump_data) #define IOCTL_OCXL_PMEM_CONTROLLER_DUMP_COMPLETE _IO(OCXL_PMEM_MAGIC, 0x04) +#define IOCTL_OCXL_PMEM_CONTROLLER_STATS _IO(OCXL_PMEM_MAGIC, 0x05) #endif /* _UAPI_OCXL_SCM_H */