[26/46] cxl/port: Record parent dport when adding ports

Message ID	20220624041950.559155-1-dan.j.williams@intel.com (mailing list archive)
State	Superseded
Headers	show Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B6181FDD; Fri, 24 Jun 2022 04:20:10 +0000 (UTC) From: Dan Williams <dan.j.williams@intel.com> To: linux-cxl@vger.kernel.org Cc: nvdimm@lists.linux.dev, linux-pci@vger.kernel.org, patches@lists.linux.dev, hch@lst.de, Dan Williams <dan.j.williams@intel.com> Subject: [PATCH 26/46] cxl/port: Record parent dport when adding ports Date: Thu, 23 Jun 2022 21:19:30 -0700 Message-Id: <20220624041950.559155-1-dan.j.williams@intel.com> In-Reply-To: <165603869943.551046.3498980330327696732.stgit@dwillia2-xfh> References: <165603869943.551046.3498980330327696732.stgit@dwillia2-xfh> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	CXL PMEM Region Provisioning \| expand [00/46] CXL PMEM Region Provisioning [01/46] tools/testing/cxl: Fix cxl_hdm_decode_init() calling convention [02/46] cxl/port: Keep port->uport valid for the entire life of a port [03/46] cxl/hdm: Use local hdm variable [04/46] cxl/core: Rename ->decoder_range ->hpa_range [05/46] cxl/core: Drop ->platform_res attribute for root decoders [06/46] cxl/core: Drop is_cxl_decoder() [07/46] cxl: Introduce cxl_to_{ways,granularity} [08/46] cxl/core: Define a 'struct cxl_switch_decoder' [09/46] cxl/acpi: Track CXL resources in iomem_resource [10/46] cxl/core: Define a 'struct cxl_root_decoder' for tracking CXL window resources [11/46] cxl/core: Define a 'struct cxl_endpoint_decoder' for tracking DPA resources [12/46] cxl/mem: Convert partition-info to resources [13/46] cxl/hdm: Require all decoders to be enumerated [14/46] cxl/hdm: Enumerate allocated DPA [15/46] cxl/Documentation: List attribute permissions [16/46] cxl/hdm: Add 'mode' attribute to decoder objects [17/46] cxl/hdm: Track next decoder to allocate [18/46] cxl/hdm: Add support for allocating DPA to an endpoint decoder [19/46] cxl/debug: Move debugfs init to cxl_core_init() [20/46] cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem' [21/46] tools/testing/cxl: Move cxl_test resources to the top of memory [22/46] tools/testing/cxl: Expand CFMWS windows [23/46] tools/testing/cxl: Add partition support [24/46] tools/testing/cxl: Fix decoder default state [25/46] cxl/port: Record dport in endpoint references [26/46] cxl/port: Record parent dport when adding ports [27/46] cxl/port: Move 'cxl_ep' references to an xarray per port [28/46] cxl/port: Move dport tracking to an xarray [29/46] cxl/port: Cache CXL host bridge data [30/46] cxl/hdm: Add sysfs attributes for interleave ways + granularity [31/46] cxl/hdm: Initialize decoder type for memory expander devices [32/46] cxl/mem: Enumerate port targets before adding endpoints [33/46] resource: Introduce alloc_free_mem_region() [34/46] cxl/region: Add region creation support [35/46] cxl/region: Add a 'uuid' attribute [36/46] cxl/region: Add interleave ways attribute [37/46] cxl/region: Allocate host physical address (HPA) capacity to new regions [38/46] cxl/region: Enable the assignment of endpoint decoders to regions [39/46] cxl/acpi: Add a host-bridge index lookup mechanism [40/46] cxl/region: Attach endpoint decoders [41/46] cxl/region: Program target lists [42/46] cxl/hdm: Commit decoder state to hardware [43/46] cxl/region: Add region driver boiler plate [44/46] cxl/pmem: Delete unused nvdimm attribute [45/46] cxl/pmem: Fix offline_nvdimm_bus() to offline by bridge [46/46] cxl/region: Introduce cxl_pmem_region objects

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index 5972f380cdf2..09fe92177d03 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -212,8 +212,7 @@ static int add_host_bridge_uport(struct device *match, void *arg) if (rc) return rc; - port = devm_cxl_add_port(host, match, dport->component_reg_phys, - root_port); + port = devm_cxl_add_port(host, match, dport->component_reg_phys, dport); if (IS_ERR(port)) return PTR_ERR(port); dev_dbg(host, "%s: add: %s\n", dev_name(match), dev_name(&port->dev)); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index c54e1dbf92cb..8f53f59dd0fa 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -526,7 +526,7 @@ static struct lock_class_key cxl_port_key; static struct cxl_port *cxl_port_alloc(struct device *uport, resource_size_t component_reg_phys, - struct cxl_port *parent_port) + struct cxl_dport *parent_dport) { struct cxl_port *port; struct device *dev; @@ -548,9 +548,12 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, * description. */ dev = &port->dev; - if (parent_port) { - dev->parent = &parent_port->dev; + if (parent_dport) { + struct cxl_port *parent_port = parent_dport->port; + port->depth = parent_port->depth + 1; + port->parent_dport = parent_dport; + dev->parent = &parent_port->dev; } else dev->parent = uport; @@ -579,24 +582,24 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, * @host: host device for devm operations * @uport: "physical" device implementing this upstream port * @component_reg_phys: (optional) for configurable cxl_port instances - * @parent_port: next hop up in the CXL memory decode hierarchy + * @parent_dport: next hop up in the CXL memory decode hierarchy */ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, resource_size_t component_reg_phys, - struct cxl_port *parent_port) + struct cxl_dport *parent_dport) { struct cxl_port *port; struct device *dev; int rc; - port = cxl_port_alloc(uport, component_reg_phys, parent_port); + port = cxl_port_alloc(uport, component_reg_phys, parent_dport); if (IS_ERR(port)) return port; dev = &port->dev; if (is_cxl_memdev(uport)) rc = dev_set_name(dev, "endpoint%d", port->id); - else if (parent_port) + else if (parent_dport) rc = dev_set_name(dev, "port%d", port->id); else rc = dev_set_name(dev, "root%d", port->id); @@ -998,7 +1001,7 @@ static void delete_endpoint(void *data) struct cxl_port *parent_port; struct device *parent; - parent_port = cxl_mem_find_port(cxlmd); + parent_port = cxl_mem_find_port(cxlmd, NULL); if (!parent_port) goto out; parent = &parent_port->dev; @@ -1133,8 +1136,8 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, { struct device *dparent = grandparent(dport_dev); struct cxl_port *port, *parent_port = NULL; + struct cxl_dport *dport, *parent_dport; resource_size_t component_reg_phys; - struct cxl_dport *dport; int rc; if (!dparent) { @@ -1148,7 +1151,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, return -ENXIO; } - parent_port = find_cxl_port(dparent, NULL); + parent_port = find_cxl_port(dparent, &parent_dport); if (!parent_port) { /* iterate to create this parent_port */ return -EAGAIN; @@ -1167,7 +1170,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, if (!port) { component_reg_phys = find_component_registers(uport_dev); port = devm_cxl_add_port(&parent_port->dev, uport_dev, - component_reg_phys, parent_port); + component_reg_phys, parent_dport); /* retry find to pick up the new dport information */ if (!IS_ERR(port)) port = find_cxl_port_at(parent_port, dport_dev, &dport); @@ -1274,9 +1277,10 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) } EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, CXL); -struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd) +struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, + struct cxl_dport **dport) { - return find_cxl_port(grandparent(&cxlmd->dev), NULL); + return find_cxl_port(grandparent(&cxlmd->dev), dport); } EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, CXL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index e654251a54dd..55d34b1576f1 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -325,6 +325,7 @@ struct cxl_nvdimm { * @id: id for port device-name * @dports: cxl_dport instances referenced by decoders * @endpoints: cxl_ep instances, endpoints that are a descendant of this port + * @parent_dport: dport that points to this port in the parent * @decoder_ida: allocator for decoder ids * @dpa_end: cursor to track highest allocated decoder for allocation ordering * @component_reg_phys: component register capability base address (optional) @@ -337,6 +338,7 @@ struct cxl_port { int id; struct list_head dports; struct list_head endpoints; + struct cxl_dport *parent_dport; struct ida decoder_ida; int dpa_end; resource_size_t component_reg_phys; @@ -391,11 +393,12 @@ int devm_cxl_register_pci_bus(struct device *host, struct device *uport, struct pci_bus *cxl_port_to_pci_bus(struct cxl_port *port); struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, resource_size_t component_reg_phys, - struct cxl_port *parent_port); + struct cxl_dport *parent_dport); struct cxl_port *find_cxl_root(struct device *dev); int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); int cxl_bus_rescan(void); -struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd); +struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, + struct cxl_dport **dport); bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd); struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 7513bea55145..2786d3402c9e 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -26,14 +26,15 @@ */ static int create_endpoint(struct cxl_memdev *cxlmd, - struct cxl_port *parent_port) + struct cxl_dport *parent_dport) { + struct cxl_port *parent_port = parent_dport->port; struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *endpoint; int rc; endpoint = devm_cxl_add_port(&parent_port->dev, &cxlmd->dev, - cxlds->component_reg_phys, parent_port); + cxlds->component_reg_phys, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); @@ -76,6 +77,7 @@ static int cxl_mem_probe(struct device *dev) { struct cxl_memdev *cxlmd = to_cxl_memdev(dev); struct cxl_port *parent_port; + struct cxl_dport *dport; struct dentry *dentry; int rc; @@ -100,7 +102,7 @@ static int cxl_mem_probe(struct device *dev) if (rc) return rc; - parent_port = cxl_mem_find_port(cxlmd); + parent_port = cxl_mem_find_port(cxlmd, &dport); if (!parent_port) { dev_err(dev, "CXL port topology not found\n"); return -ENXIO; @@ -114,7 +116,7 @@ static int cxl_mem_probe(struct device *dev) goto unlock; } - rc = create_endpoint(cxlmd, parent_port); + rc = create_endpoint(cxlmd, dport); unlock: device_unlock(&parent_port->dev); put_device(&parent_port->dev);

[26/46] cxl/port: Record parent dport when adding ports

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