Message ID | 20220929073259.582822-1-rvkagan@yandex-team.ru (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drivers/nvdimm/e820: turn off write cache by default | expand |
diff --git a/drivers/nvdimm/e820.c b/drivers/nvdimm/e820.c index 4cd18be9d0e9..3af63b7b6d23 100644 --- a/drivers/nvdimm/e820.c +++ b/drivers/nvdimm/e820.c @@ -28,6 +28,7 @@ static int e820_register_one(struct resource *res, void *data) ndr_desc.numa_node = numa_map_to_online_node(nid); ndr_desc.target_node = nid; set_bit(ND_REGION_PAGEMAP, &ndr_desc.flags); + set_bit(ND_REGION_PERSIST_CACHE, &ndr_desc.flags); if (!nvdimm_pmem_region_create(nvdimm_bus, &ndr_desc)) return -ENXIO; return 0;
When regular DRAM is registered for use as PMEM via "memmap" command line parameter, there's no write cache in front of the backing store of this PMEM (as there's no backing store itself), so there's no point doing expensive cache flush on sync etc. Mark the regions being registered with e820 as ND_REGION_PERSIST_CACHE so that write cache is off by default for the respective DAX devices. This also matches the assumed behavior of the flag ND_REGION_PERSIST_CACHE: Platform ensures entire CPU store data path is flushed to pmem on system power loss. for the only usecase where such regions actually kind of persist the data -- across kexec. Signed-off-by: Roman Kagan <rvkagan@yandex-team.ru> --- drivers/nvdimm/e820.c | 1 + 1 file changed, 1 insertion(+)