From patchwork Tue Oct 29 20:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 13855413 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA19B207A34 for ; Tue, 29 Oct 2024 20:35:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730234141; cv=none; b=T5JKN5bjju1N+v+RsWyvfwLTfka7I4Jrxx2PEgH7MSLoYC8MTiH/bRzl78rUZa55JSVdfbcIHjxAookXZFS7S2MURAK/D8wq3W0Gh7d+B43i47so1/pqksdr4BUspJ8fdPh1OiT4ikt6glBWbbj515fztyFPq9IovoySMVc6ytU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730234141; c=relaxed/simple; bh=w6eMufTjqClyKo67DpOPZ8BbObwGk8D8vaISnd0YkAM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f4eN8CpdXquH/AzQxrUJ4MHgcAV0L0g2fXe4ZXs0FvvcS4MH92lyzUWGa2FhZNyye9N90DhFxqntCQe10gufiNNdVsSnaHah4Lf3GEpClk2dsscnDPrWNMDS3oCBerYiU/fsvVg15UgxbV3UkwxaExZu95ymQKWtPDX9uEoZuoE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RNCkYwfI; arc=none smtp.client-ip=192.198.163.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RNCkYwfI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1730234140; x=1761770140; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=w6eMufTjqClyKo67DpOPZ8BbObwGk8D8vaISnd0YkAM=; b=RNCkYwfI+LOa8cuJwg/yi6s49iZIXEdwCA5a2RLmQl6YSgXZKpvNbbWs MWk4PpvV3PAiNIm8suhu7YnwzIur+OUzfuJtl/0FcEu6qHOTgwU+F+i7d 6g5zmzeMS7GumS3BCtGo/FLvr8trGwNZSeiFB3oMNYhG/VFlDdcPZU6y4 nSWY9qV0KsiajZVi2IUhTbcEBfADkF9Sfl+84rqzK+bZHDAuZi3uuMZmn JhCvKqrWOE2eFLksKoXT5aG1U5uPticx6BnXVuQGdlFIRt1hp7MeM/HCI YbmkBbnLVZSAzggQWAwhsH5jqXM4h4IQG3Bw8Pbc6+divY7Sb8EZjWdj3 w==; X-CSE-ConnectionGUID: Bnj6nSO2S06KY7kt7D+10Q== X-CSE-MsgGUID: vKQaUsayTeifrJeGbBxCAw== X-IronPort-AV: E=McAfee;i="6700,10204,11240"; a="40485446" X-IronPort-AV: E=Sophos;i="6.11,243,1725346800"; d="scan'208";a="40485446" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 13:35:39 -0700 X-CSE-ConnectionGUID: Z00oaTMVR96uY5Y+19BAsQ== X-CSE-MsgGUID: eQ2CNOZ5Rqa7MJr00kvdSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,243,1725346800"; d="scan'208";a="82185288" Received: from ldmartin-desk2.corp.intel.com (HELO localhost) ([10.125.108.77]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2024 13:35:36 -0700 From: ira.weiny@intel.com Date: Tue, 29 Oct 2024 15:34:45 -0500 Subject: [PATCH v5 10/27] cxl/region: Add dynamic capacity decoder and region modes Precedence: bulk X-Mailing-List: nvdimm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241029-dcd-type2-upstream-v5-10-8739cb67c374@intel.com> References: <20241029-dcd-type2-upstream-v5-0-8739cb67c374@intel.com> In-Reply-To: <20241029-dcd-type2-upstream-v5-0-8739cb67c374@intel.com> To: Dave Jiang , Fan Ni , Jonathan Cameron , Navneet Singh , Jonathan Corbet , Andrew Morton Cc: Dan Williams , Davidlohr Bueso , Alison Schofield , Vishal Verma , Ira Weiny , linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org, nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org, Li Ming X-Mailer: b4 0.15-dev-2a633 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730234086; l=3549; i=ira.weiny@intel.com; s=20221211; h=from:subject:message-id; bh=i85C72bQ7gS6gmTgL5MUvGonqr0KyV1ZCwFvrUhKsoo=; b=hHX7UVTJMp1JyiI9cWae9grQD3N7iYmVaIGu/9TUnZUV8QYcQVNJbOxktnbWK3QjY7sU+bOGS 3umjm9w2A3RB60sQo5rmOQ4BM9NpS1d1Ri0a9Ws9SJDZ8pjPJnQT9Qq X-Developer-Key: i=ira.weiny@intel.com; a=ed25519; pk=noldbkG+Wp1qXRrrkfY1QJpDf7QsOEthbOT7vm0PqsE= From: Navneet Singh One or more decoders each pointing to a Dynamic Capacity (DC) partition form a CXL software region. The region mode reflects composition of that entire software region. Decoder mode reflects a specific DC partition. DC partitions are also known as DC regions per CXL specification v3.1. Define the new modes and helper functions required to make the association between these new modes. Reviewed-by: Jonathan Cameron Reviewed-by: Fan Ni Signed-off-by: Navneet Singh Reviewed-by: Dave Jiang Reviewed-by: Li Ming Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny --- Changes: [iweiny: keep tags on simple patch] [Fan: s/partitions/partition/] [djiang: New wording for the commit message] [iweiny: reword commit message more] --- drivers/cxl/core/region.c | 4 ++++ drivers/cxl/cxl.h | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index b3beab787faeb552850ac3839472319fcf8f2835..2ca6148d108cc020bebcb34b09028fa59bb62f02 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1870,6 +1870,8 @@ static bool cxl_modes_compatible(enum cxl_region_mode rmode, return true; if (rmode == CXL_REGION_PMEM && dmode == CXL_DECODER_PMEM) return true; + if (rmode == CXL_REGION_DC && cxl_decoder_mode_is_dc(dmode)) + return true; return false; } @@ -3233,6 +3235,8 @@ cxl_decoder_to_region_mode(enum cxl_decoder_mode mode) return CXL_REGION_RAM; case CXL_DECODER_PMEM: return CXL_REGION_PMEM; + case CXL_DECODER_DC0 ... CXL_DECODER_DC7: + return CXL_REGION_DC; case CXL_DECODER_MIXED: default: return CXL_REGION_MIXED; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 5d74eb4ffab3ea2656c8e3c0563b8d7b69d76232..f931ebdd36d05a8aa758627746f0fa425a5f14fd 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -370,6 +370,14 @@ enum cxl_decoder_mode { CXL_DECODER_NONE, CXL_DECODER_RAM, CXL_DECODER_PMEM, + CXL_DECODER_DC0, + CXL_DECODER_DC1, + CXL_DECODER_DC2, + CXL_DECODER_DC3, + CXL_DECODER_DC4, + CXL_DECODER_DC5, + CXL_DECODER_DC6, + CXL_DECODER_DC7, CXL_DECODER_MIXED, CXL_DECODER_DEAD, }; @@ -380,6 +388,14 @@ static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) [CXL_DECODER_NONE] = "none", [CXL_DECODER_RAM] = "ram", [CXL_DECODER_PMEM] = "pmem", + [CXL_DECODER_DC0] = "dc0", + [CXL_DECODER_DC1] = "dc1", + [CXL_DECODER_DC2] = "dc2", + [CXL_DECODER_DC3] = "dc3", + [CXL_DECODER_DC4] = "dc4", + [CXL_DECODER_DC5] = "dc5", + [CXL_DECODER_DC6] = "dc6", + [CXL_DECODER_DC7] = "dc7", [CXL_DECODER_MIXED] = "mixed", }; @@ -388,10 +404,16 @@ static inline const char *cxl_decoder_mode_name(enum cxl_decoder_mode mode) return "mixed"; } +static inline bool cxl_decoder_mode_is_dc(enum cxl_decoder_mode mode) +{ + return (mode >= CXL_DECODER_DC0 && mode <= CXL_DECODER_DC7); +} + enum cxl_region_mode { CXL_REGION_NONE, CXL_REGION_RAM, CXL_REGION_PMEM, + CXL_REGION_DC, CXL_REGION_MIXED, }; @@ -401,6 +423,7 @@ static inline const char *cxl_region_mode_name(enum cxl_region_mode mode) [CXL_REGION_NONE] = "none", [CXL_REGION_RAM] = "ram", [CXL_REGION_PMEM] = "pmem", + [CXL_REGION_DC] = "dc", [CXL_REGION_MIXED] = "mixed", };