@@ -104,31 +104,6 @@ HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
return status;
}
-/* Reads the full status register for mailbox. */
-HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
- u32 *const pIsFull)
-{
- HW_STATUS status = RET_OK;
- u32 fullStatus;
-
- /* Check input parameters */
- CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
- RES_INVALID_INPUT_PARAM);
- CHECK_INPUT_PARAM(pIsFull, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
- RES_INVALID_INPUT_PARAM);
- CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
- RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
-
- /* read the is full status parameter for Mailbox */
- fullStatus = MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress,
- (u32)mailBoxId);
-
- /* fill in return parameter */
- *pIsFull = (fullStatus & 0xFF);
-
- return status;
-}
-
/* Gets number of messages in a specified mailbox. */
HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
u32 *const pNumMsg)
@@ -130,41 +130,6 @@ extern HW_STATUS HW_MBOX_MsgWrite(
);
/*
-* FUNCTION : HW_MBOX_IsFull
-*
-* INPUTS:
-*
-* Identifier : baseAddress
-* Type : const u32
-* Description : Base Address of instance of Mailbox module
-*
-* Identifier : mailBoxId
-* Type : const HW_MBOX_Id_t
-* Description : Mail Box Sub module Id to check
-*
-* OUTPUTS:
-*
-* Identifier : pIsFull
-* Type : u32 *const
-* Description : false means mail box not Full
-* true means mailbox full.
-*
-* RETURNS:
-*
-* Type : ReturnCode_t
-* Description : RET_OK No errors occured
-* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
-* RET_INVALID_ID Invalid Id used
-*
-* PURPOSE: : this function reads the full status register for mailbox.
-*/
-extern HW_STATUS HW_MBOX_IsFull(
- const u32 baseAddress,
- const HW_MBOX_Id_t mailBoxId,
- u32 *const pIsFull
- );
-
-/*
* FUNCTION : HW_MBOX_NumMsgGet
*
* INPUTS:
@@ -28,6 +28,13 @@
extern struct platform_device omap_dspbridge_dev;
#endif
+#define MAILBOX_FIFOSTATUS(m) (0x80 + 4 * (m))
+
+static inline unsigned int fifo_full(void __iomem *mbox_base, int mbox_id)
+{
+ return __raw_readb(mbox_base + MAILBOX_FIFOSTATUS(mbox_id)) & 0x1;
+}
+
DSP_STATUS CHNLSM_EnableInterrupt(struct WMD_DEV_CONTEXT *pDevContext)
{
DSP_STATUS status = DSP_SOK;
@@ -97,7 +104,6 @@ DSP_STATUS CHNLSM_InterruptDSP(struct WMD_DEV_CONTEXT *pDevContext)
omap_dspbridge_dev.dev.platform_data;
u32 opplevel = 0;
#endif
- u32 mbxFull;
struct CFG_HOSTRES resources;
u16 cnt = 10;
u32 temp;
@@ -137,17 +143,12 @@ DSP_STATUS CHNLSM_InterruptDSP(struct WMD_DEV_CONTEXT *pDevContext)
pDevContext->dwBrdState = BRD_RUNNING;
}
- while (--cnt) {
- HW_MBOX_IsFull(resources.dwMboxBase,
- MBOX_ARM2DSP, &mbxFull);
- if (mbxFull)
- mdelay(1);
- else
- break;
- }
- if (!cnt) {
- DBG_Trace(DBG_LEVEL7, "Timed out waiting for DSP mailbox \n");
- return WMD_E_TIMEOUT;
+ while (fifo_full((void __iomem *) resources.dwMboxBase, 0)) {
+ if (--cnt == 0) {
+ DBG_Trace(DBG_LEVEL7, "Timed out waiting for DSP mailbox \n");
+ return WMD_E_TIMEOUT;
+ }
+ mdelay(1);
}
DBG_Trace(DBG_LEVEL3, "writing %x to Mailbox\n",
pDevContext->wIntrVal2Dsp);