diff mbox

OMAP3: PM: SDRC: ensure mux of SDRC clock enable pins for self-refresh

Message ID 1242835699-11113-1-git-send-email-khilman@deeprootsystems.com (mailing list archive)
State Awaiting Upstream, archived
Headers show

Commit Message

Kevin Hilman May 20, 2009, 4:08 p.m. UTC
For SDRAM self-refresh to work properly, the SDRC clock-enable pins
for both chip selects must be mux'd properly.

Since these pins are not shared with anything else (according to ES3.1
TRM ver. P), they should always be mux'd in the SDRC mode (mode 0.)

Special thanks to Paul Walmsley for pointing this out.

Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
---
 arch/arm/mach-omap2/mux.c             |    5 +++++
 arch/arm/mach-omap2/sdrc.c            |    8 ++++++++
 arch/arm/plat-omap/include/mach/mux.h |    3 +++
 3 files changed, 16 insertions(+), 0 deletions(-)

Comments

Paul Walmsley May 21, 2009, 10:37 p.m. UTC | #1
Hi Kevin

On Wed, 20 May 2009, Kevin Hilman wrote:

> diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> index c832d83..d7807e2 100644
> --- a/arch/arm/mach-omap2/sdrc.c
> +++ b/arch/arm/mach-omap2/sdrc.c
> @@ -136,5 +136,13 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
>  		(1 << SDRC_POWER_PWDENA_SHIFT) |
>  		(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
>  	sdrc_write_reg(l, SDRC_POWER);
> +
> +	/* Ensure SDRC pins for both chip selcts are mux'd properly
> +	 * for self-refresh */
> +	if (cpu_is_omap34xx()) {
> +		omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +		omap_cfg_reg(H17_34XX_SDRC_CKE1);
> +	}
> +
>  	omap2_sms_save_context();
>  }

would suggest keeping pin remuxing in board-*.c or maybe chip-*.c files; 
ideally this file would only pertain to the SDRC IP block itself.


- Paul
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Mike Chan May 21, 2009, 11:17 p.m. UTC | #2
On Thu, May 21, 2009 at 3:37 PM, Paul Walmsley <paul@pwsan.com> wrote:
>
> Hi Kevin
>
> On Wed, 20 May 2009, Kevin Hilman wrote:
>
> > diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
> > index c832d83..d7807e2 100644
> > --- a/arch/arm/mach-omap2/sdrc.c
> > +++ b/arch/arm/mach-omap2/sdrc.c
> > @@ -136,5 +136,13 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
> >               (1 << SDRC_POWER_PWDENA_SHIFT) |
> >               (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
> >       sdrc_write_reg(l, SDRC_POWER);
> > +
> > +     /* Ensure SDRC pins for both chip selcts are mux'd properly
> > +      * for self-refresh */
> > +     if (cpu_is_omap34xx()) {
> > +             omap_cfg_reg(H16_34XX_SDRC_CKE0);
> > +             omap_cfg_reg(H17_34XX_SDRC_CKE1);
> > +     }
> > +
> >       omap2_sms_save_context();
> >  }
>
> would suggest keeping pin remuxing in board-*.c or maybe chip-*.c files;
> ideally this file would only pertain to the SDRC IP block itself.
>
>
> - Paul

Is there a reason why any board-*.c would not want this? It seems a
little silly for everyone to be doing the same repetitive pin muxing
if they want to suspend properly for a reasonable amount of time.

- Mike
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Paul Walmsley May 21, 2009, 11:46 p.m. UTC | #3
On Thu, 21 May 2009, Mike Chan wrote:

> On Thu, May 21, 2009 at 3:37 PM, Paul Walmsley <paul@pwsan.com> wrote:
> >
> > would suggest keeping pin remuxing in board-*.c or maybe chip-*.c files;
> > ideally this file would only pertain to the SDRC IP block itself.
> 
> Is there a reason why any board-*.c would not want this? It seems a
> little silly for everyone to be doing the same repetitive pin muxing
> if they want to suspend properly for a reasonable amount of time.

I suspect you are asking a slightly different question, which is, "why 
shouldn't this pin muxing go in sdrc.c".  The reason is because the pin 
muxing API we have is chip- and package-specific.  This sdrc.c file 
shouldn't contain any chip- or package-specific information.  Whether it 
goes into board-*.c or into a chip- or package-specific file is another 
question.

Richard's earlier E-mail covered the answer to your literal question.  It 
seems wisest for boards that don't use SDRC_CKE1 to keep it in safe mode.


- Paul
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diff mbox

Patch

diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 026c4fc..4ed8047 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -486,6 +486,11 @@  MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
 MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
 		OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
+
+MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
+MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
+		OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
 };
 
 #define OMAP34XX_PINS_SZ	ARRAY_SIZE(omap34xx_pins)
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index c832d83..d7807e2 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -136,5 +136,13 @@  void __init omap2_sdrc_init(struct omap_sdrc_params *sp)
 		(1 << SDRC_POWER_PWDENA_SHIFT) |
 		(1 << SDRC_POWER_PAGEPOLICY_SHIFT);
 	sdrc_write_reg(l, SDRC_POWER);
+
+	/* Ensure SDRC pins for both chip selcts are mux'd properly
+	 * for self-refresh */
+	if (cpu_is_omap34xx()) {
+		omap_cfg_reg(H16_34XX_SDRC_CKE0);
+		omap_cfg_reg(H17_34XX_SDRC_CKE1);
+	}
+
 	omap2_sms_save_context();
 }
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index f7e298a..9795d8d 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -803,6 +803,9 @@  enum omap34xx_index {
 	AE5_34XX_GPIO143,
 	H19_34XX_GPIO164_OUT,
 	J25_34XX_GPIO170,
+
+	H16_34XX_SDRC_CKE0,
+	H17_34XX_SDRC_CKE1,
 };
 
 struct omap_mux_cfg {