From patchwork Wed May 20 16:08:19 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 25013 Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n4KG8Oet014970 for ; Wed, 20 May 2009 16:08:24 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753013AbZETQIV (ORCPT ); Wed, 20 May 2009 12:08:21 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753035AbZETQIV (ORCPT ); Wed, 20 May 2009 12:08:21 -0400 Received: from wf-out-1314.google.com ([209.85.200.173]:37448 "EHLO wf-out-1314.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752412AbZETQIV (ORCPT ); Wed, 20 May 2009 12:08:21 -0400 Received: by wf-out-1314.google.com with SMTP id 26so177482wfd.4 for ; Wed, 20 May 2009 09:08:22 -0700 (PDT) Received: by 10.142.193.10 with SMTP id q10mr482825wff.274.1242835702350; Wed, 20 May 2009 09:08:22 -0700 (PDT) Received: from localhost ([216.254.16.51]) by mx.google.com with ESMTPS id 30sm551368wfc.18.2009.05.20.09.08.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 20 May 2009 09:08:21 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org Cc: mikechan@google.com, Kevin Hilman , Paul Walmsley Subject: [PATCH] OMAP3: PM: SDRC: ensure mux of SDRC clock enable pins for self-refresh Date: Wed, 20 May 2009 09:08:19 -0700 Message-Id: <1242835699-11113-1-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.6.2.2 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org For SDRAM self-refresh to work properly, the SDRC clock-enable pins for both chip selects must be mux'd properly. Since these pins are not shared with anything else (according to ES3.1 TRM ver. P), they should always be mux'd in the SDRC mode (mode 0.) Special thanks to Paul Walmsley for pointing this out. Cc: Paul Walmsley Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/mux.c | 5 +++++ arch/arm/mach-omap2/sdrc.c | 8 ++++++++ arch/arm/plat-omap/include/mach/mux.h | 3 +++ 3 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 026c4fc..4ed8047 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -486,6 +486,11 @@ MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) + +MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) +MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264, + OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT) }; #define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins) diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index c832d83..d7807e2 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -136,5 +136,13 @@ void __init omap2_sdrc_init(struct omap_sdrc_params *sp) (1 << SDRC_POWER_PWDENA_SHIFT) | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); sdrc_write_reg(l, SDRC_POWER); + + /* Ensure SDRC pins for both chip selcts are mux'd properly + * for self-refresh */ + if (cpu_is_omap34xx()) { + omap_cfg_reg(H16_34XX_SDRC_CKE0); + omap_cfg_reg(H17_34XX_SDRC_CKE1); + } + omap2_sms_save_context(); } diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h index f7e298a..9795d8d 100644 --- a/arch/arm/plat-omap/include/mach/mux.h +++ b/arch/arm/plat-omap/include/mach/mux.h @@ -803,6 +803,9 @@ enum omap34xx_index { AE5_34XX_GPIO143, H19_34XX_GPIO164_OUT, J25_34XX_GPIO170, + + H16_34XX_SDRC_CKE0, + H17_34XX_SDRC_CKE1, }; struct omap_mux_cfg {