| Message ID | 1248958183-15015-7-git-send-email-eduardo.valentin@nokia.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
On Thu, 30 Jul 2009 15:49:29 +0300 Eduardo Valentin <eduardo.valentin@nokia.com> wrote: > --- a/arch/arm/plat-omap/mcbsp.c > +++ b/arch/arm/plat-omap/mcbsp.c > @@ -394,7 +394,8 @@ void omap_mcbsp_start(unsigned int id) > w = OMAP_MCBSP_READ(io_base, SPCR1); > OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1); > > - udelay(100); > + /* Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec */ > + udelay(500); > Note: udelay(100) us used to wait at least 2 CLKSRG cycles (as stated in TRM). Are you sure this change is necessary? CLKSRG is kind of master clock to McBSP so original stetson guessed (?) 100 us should be fine for all serial links where bit clock is higher than 20 kHz.
Jarkko Nikula [jhnikula@gmail.com] wrote: > Are you sure this change is necessary? CLKSRG is kind of master clock > to McBSP so original stetson guessed (?) 100 us should be fine for all > serial links where bit clock is higher than 20 kHz. The McBSP / DMA stuff doesn't really work properly, when PM is enabled to full extent. The first DMA goes in _before_ the omap_mcbsp_start(), so the higher delay compensates DMA misbehavior in a way... .. L/R channels also may switch at random initially with full PM enabled. So the L/R fix is only working, if no PM is enabled (sigh). Need to make that work fine (no L/R switching and early no DMA completions) to get rid of the higher, 500us, timeout. Maybe try not having XCCR/RCCR dma enable bit initially, but enabling them at omap_mcbsp_start()? (I'd try if I wasn't also on vacation). - Eero-- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, 31 Jul 2009 09:21:30 +0200 <ext-Eero.Nurkkala@nokia.com> wrote: > Jarkko Nikula [jhnikula@gmail.com] wrote: > > Are you sure this change is necessary? CLKSRG is kind of master > > clock to McBSP so original stetson guessed (?) 100 us should be > > fine for all serial links where bit clock is higher than 20 kHz. > > The McBSP / DMA stuff doesn't really work properly, when PM is enabled > to full extent. The first DMA goes in _before_ the omap_mcbsp_start(), > so the higher delay compensates DMA misbehavior in a way... > > .. L/R channels also may switch at random initially with full PM > enabled. So the L/R fix is only working, if no PM is enabled (sigh). > > Need to make that work fine (no L/R switching and early no DMA > completions) to get rid of the higher, 500us, timeout. Maybe try not > having XCCR/RCCR dma enable bit initially, but enabling them at > omap_mcbsp_start()? (I'd try if I wasn't also on vacation). > Ok, 500 us is not so long delay here compared to benefits but it would be good to have a little revisit comment for future reference. I think that by default 100 us provides enough time for two CLKSRG cycles but due some unknown PM related, clock gating etc. reason it must be extended to 500 us now.
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 6b39656..373926d 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -394,7 +394,8 @@ void omap_mcbsp_start(unsigned int id) w = OMAP_MCBSP_READ(io_base, SPCR1); OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1); - udelay(100); + /* Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec */ + udelay(500); /* Start frame sync */ w = OMAP_MCBSP_READ(io_base, SPCR2);
Signed-off-by: Eduardo Valentin <eduardo.valentin@nokia.com> --- arch/arm/plat-omap/mcbsp.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)