@@ -680,6 +680,7 @@
#define OMAP3430_CLKSEL_GPT2_SHIFT 0
/* CM_SLEEPDEP_PER specific bits */
+#define OMAP3430_CM_SLEEPDEP_PER_EN_MPU (1 << 1)
#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
/* CM_CLKSTCTRL_PER */
@@ -26,6 +26,7 @@
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <mach/sram.h>
#include <mach/prcm.h>
@@ -934,6 +935,24 @@ static void __init prcm_setup_regs(void)
prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
if (omap_rev() > OMAP3430_REV_ES1_0) {
+
+ /*
+ * This workaround is needed to prevent SGX and USBHOST from
+ * failing to transition to RET/OFF after a warm reset in OFF
+ * mode. Workaround sets a sleepdep of each of these domains
+ * with MPU, waits for a min 2 sysclk cycles and clears the
+ * sleepdep.
+ */
+ cm_write_mod_reg(OMAP3430_CM_SLEEPDEP_PER_EN_MPU,
+ OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
+ cm_write_mod_reg(OMAP3430_CM_SLEEPDEP_PER_EN_MPU,
+ OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
+ udelay(100);
+ cm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD,
+ OMAP3430_CM_SLEEPDEP);
+ cm_write_mod_reg(0, OMAP3430ES2_SGX_MOD,
+ OMAP3430_CM_SLEEPDEP);
+
prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
} else