From patchwork Fri Oct 16 10:48:55 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 54222 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n9GB8hRW026877 for ; Fri, 16 Oct 2009 11:08:44 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758292AbZJPLEb (ORCPT ); Fri, 16 Oct 2009 07:04:31 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1758223AbZJPLEb (ORCPT ); Fri, 16 Oct 2009 07:04:31 -0400 Received: from smtp.nokia.com ([192.100.122.233]:32281 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756905AbZJPLE3 (ORCPT ); Fri, 16 Oct 2009 07:04:29 -0400 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9GB2f4k011809 for ; Fri, 16 Oct 2009 14:03:01 +0300 Received: from vaebh104.NOE.Nokia.com ([10.160.244.30]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Oct 2009 14:02:46 +0300 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by vaebh104.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Oct 2009 14:02:45 +0300 Received: from localhost.localdomain (sokoban.ntc.nokia.com [172.22.144.95]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id n9GB2fZu022261 for ; Fri, 16 Oct 2009 14:02:44 +0300 From: Tero Kristo To: linux-omap@vger.kernel.org Subject: [PATCH 02/17] OMAP3: PM: Dynamic check for CORE target state Date: Fri, 16 Oct 2009 13:48:55 +0300 Message-Id: <1255690150-16853-3-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1255690150-16853-2-git-send-email-tero.kristo@nokia.com> References: <> <1255690150-16853-1-git-send-email-tero.kristo@nokia.com> <1255690150-16853-2-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 16 Oct 2009 11:02:45.0474 (UTC) FILETIME=[30B10C20:01CA4E50] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index a2fcfcc..715ab14 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -76,6 +76,7 @@ #define OMAP3430ES2_CM_CLKEN2 0x0004 #define OMAP3430ES2_CM_FCLKEN3 0x0008 #define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 +#define OMAP3430_CM_IDLEST3 0x0028 #define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 #define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 #define OMAP3430_CM_CLKSEL1 CM_CLKSEL diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 5e2ef63..e8704a6 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -64,6 +64,28 @@ u32 sleep_while_idle; u32 wakeup_timer_seconds; u32 voltage_off_while_idle; +/* IDLEST bitmasks for core status checks */ +#define CORE_IDLEST1_ALL (\ + OMAP3430ES2_ST_MMC3_MASK|OMAP3430_ST_ICR_MASK|\ + OMAP3430_ST_AES2_MASK|OMAP3430_ST_SHA12_MASK|\ + OMAP3430_ST_DES2_MASK|OMAP3430_ST_MMC2_MASK|\ + OMAP3430_ST_MMC1_MASK|OMAP3430_ST_MSPRO_MASK|\ + OMAP3430_ST_HDQ_MASK|OMAP3430_ST_MCSPI4_MASK|\ + OMAP3430_ST_MCSPI3_MASK|OMAP3430_ST_MCSPI2_MASK|\ + OMAP3430_ST_MCSPI1_MASK|OMAP3430_ST_I2C3_MASK|\ + OMAP3430_ST_I2C2_MASK|OMAP3430_ST_I2C1_MASK|\ + OMAP3430_ST_GPT11_MASK|OMAP3430_ST_GPT10_MASK|\ + OMAP3430_ST_MCBSP5_MASK|OMAP3430_ST_MCBSP1_MASK|\ + OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK|\ + OMAP3430ES2_ST_SSI_IDLE_MASK|OMAP3430_ST_SDMA_MASK|\ + OMAP3430_ST_SSI_STDBY_MASK|OMAP3430_ST_D2D_MASK) +#define CORE_IDLEST2_ALL (\ + OMAP3430_ST_PKA_MASK|OMAP3430_ST_AES1_MASK|\ + OMAP3430_ST_RNG_MASK|OMAP3430_ST_SHA11_MASK|\ + OMAP3430_ST_DES1_MASK) +#define CORE_IDLEST3_ALL (\ + OMAP3430ES2_ST_USBTLL_MASK|OMAP3430ES2_ST_CPEFUSE_MASK) + struct power_state { struct powerdomain *pwrdm; u32 next_state; @@ -408,6 +430,7 @@ void omap_sram_idle(void) int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; int per_state_modified = 0; + int core_saved_state = PWRDM_POWER_ON; if (!_omap_sram_idle) return; @@ -439,9 +462,28 @@ void omap_sram_idle(void) if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); + /* + * Check whether core will enter idle or not. This is needed + * because I/O pad wakeup will fail if core stays on and PER + * enters off. This will also prevent unnecessary core context + * save / restore. + */ + core_next_state = pwrdm_read_next_pwrst(core_pwrdm); + if (core_next_state < PWRDM_POWER_ON) { + core_saved_state = core_next_state; + if ((cm_read_mod_reg(CORE_MOD, CM_IDLEST1) & CORE_IDLEST1_ALL) + != CORE_IDLEST1_ALL || + (cm_read_mod_reg(CORE_MOD, CM_IDLEST2) & CORE_IDLEST2_ALL) + != CORE_IDLEST2_ALL || + (cm_read_mod_reg(CORE_MOD, OMAP3430_CM_IDLEST3) & + CORE_IDLEST3_ALL) != CORE_IDLEST3_ALL) { + core_next_state = PWRDM_POWER_ON; + pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); + } + } + /* PER */ per_next_state = pwrdm_read_next_pwrst(per_pwrdm); - core_next_state = pwrdm_read_next_pwrst(core_pwrdm); if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); omap2_gpio_prepare_for_idle(per_next_state); @@ -539,6 +581,8 @@ void omap_sram_idle(void) enable_smartreflex(SR1); enable_smartreflex(SR2); } + if (core_saved_state != core_next_state) + pwrdm_set_next_pwrst(core_pwrdm, core_saved_state); /* PER */ if (per_next_state < PWRDM_POWER_ON) {