From patchwork Thu Nov 12 17:02:36 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 59603 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id nACHL8Mb004172 for ; Thu, 12 Nov 2009 17:21:09 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753835AbZKLRUb (ORCPT ); Thu, 12 Nov 2009 12:20:31 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1753822AbZKLRUa (ORCPT ); Thu, 12 Nov 2009 12:20:30 -0500 Received: from smtp.nokia.com ([192.100.105.134]:43815 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753835AbZKLRU2 (ORCPT ); Thu, 12 Nov 2009 12:20:28 -0500 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id nACHJCB6025817; Thu, 12 Nov 2009 11:20:24 -0600 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 12 Nov 2009 19:19:55 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 12 Nov 2009 19:19:55 +0200 Received: from localhost.localdomain (sokoban.ntc.nokia.com [172.22.144.95]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id nACHJoNa020986; Thu, 12 Nov 2009 19:19:54 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com Subject: [PATCH 3/6] OMAP3: CPUidle: Fixed support for ON / INACTIVE states Date: Thu, 12 Nov 2009 19:02:36 +0200 Message-Id: <1258045359-7962-4-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1258045359-7962-3-git-send-email-tero.kristo@nokia.com> References: <> <1258045359-7962-1-git-send-email-tero.kristo@nokia.com> <1258045359-7962-2-git-send-email-tero.kristo@nokia.com> <1258045359-7962-3-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 12 Nov 2009 17:19:55.0952 (UTC) FILETIME=[5AA93300:01CA63BC] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index fdfa1d5..e46345f 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -91,20 +91,6 @@ static int omap3_idle_bm_check(void) return 0; } -static int _cpuidle_allow_idle(struct powerdomain *pwrdm, - struct clockdomain *clkdm) -{ - omap2_clkdm_allow_idle(clkdm); - return 0; -} - -static int _cpuidle_deny_idle(struct powerdomain *pwrdm, - struct clockdomain *clkdm) -{ - omap2_clkdm_deny_idle(clkdm); - return 0; -} - /** * omap3_enter_idle - Programs OMAP3 to enter the specified state * @dev: cpuidle device @@ -141,19 +127,9 @@ static int omap3_enter_idle(struct cpuidle_device *dev, if (omap_irq_pending() || need_resched()) goto return_sleep_time; - if (cx->type == OMAP3_STATE_C1) { - pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); - pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); - } - /* Execute ARM wfi */ omap_sram_idle(); - if (cx->type == OMAP3_STATE_C1) { - pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); - pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); - } - return_sleep_time: getnstimeofday(&ts_postidle); ts_idle = timespec_sub(ts_postidle, ts_preidle); @@ -242,8 +218,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].wake_latency; omap3_power_states[OMAP3_STATE_C2].threshold = cpuidle_params_table[OMAP3_STATE_C2].threshold; - omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_INACTIVE; + omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; /* C3 . MPU CSWR + Core inactive */ @@ -256,7 +232,7 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C3].threshold = cpuidle_params_table[OMAP3_STATE_C3].threshold; omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; - omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; @@ -270,7 +246,7 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C4].threshold = cpuidle_params_table[OMAP3_STATE_C4].threshold; omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; - omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM;