From patchwork Wed Dec 16 13:57:03 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ranjith Lohithakshan X-Patchwork-Id: 68364 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id nBI4ixoE005715 for ; Fri, 18 Dec 2009 04:46:10 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933081AbZLPN5M (ORCPT ); Wed, 16 Dec 2009 08:57:12 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S933068AbZLPN5L (ORCPT ); Wed, 16 Dec 2009 08:57:11 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:40151 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932972AbZLPN5K (ORCPT ); Wed, 16 Dec 2009 08:57:10 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id nBGDv6Yl032163 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 16 Dec 2009 07:57:08 -0600 Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id nBGDv3EP017768; Wed, 16 Dec 2009 19:27:04 +0530 (IST) Received: from psplinux050.india.ti.com (localhost [127.0.0.1]) by psplinux050.india.ti.com (8.13.1/8.13.1) with ESMTP id nBGDv3Np009342; Wed, 16 Dec 2009 19:27:03 +0530 Received: (from a0876318@localhost) by psplinux050.india.ti.com (8.13.1/8.13.1/Submit) id nBGDv3YP009339; Wed, 16 Dec 2009 19:27:03 +0530 From: Ranjith Lohithakshan To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, ranjithl@ti.com Subject: [PATCH] AM35xx: Add clock support for new modules on AM35xx Date: Wed, 16 Dec 2009 19:27:03 +0530 Message-Id: <1260971823-8532-1-git-send-email-ranjithl@ti.com> X-Mailer: git-send-email 1.6.2.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/clock34xx_data.c b/arch/arm/mach-omap2/clock34xx_data.c index 043caed..d7942b3 100644 --- a/arch/arm/mach-omap2/clock34xx_data.c +++ b/arch/arm/mach-omap2/clock34xx_data.c @@ -2983,6 +2983,91 @@ static struct clk wdt1_fck = { .recalc = &followparent_recalc, }; +/* Clocks for AM35XX */ +static struct clk emac_ick = { + .name = "emac_ick", + .ops = &clkops_omap2_dflt, + .parent = &core_l3_ick, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_CPGMAC_VBUSP_CLK_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk emac_fck = { + .name = "emac_fck", + .ops = &clkops_omap2_dflt, + .clkdm_name = "core_l3_clkdm", + .rate = 50000000, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_CPGMAC_FCLK_SHIFT, + .recalc = &omap2_clksel_recalc, +}; + +static struct clk hsotgusb_ick_am35xx = { + .name = "hsotgusb_ick", + .ops = &clkops_omap2_dflt, + .parent = &core_l3_ick, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_USBOTG_VBUSP_CLK_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk hsotgusb_fck_am35xx = { + .name = "hsotgusb_fck", + .ops = &clkops_omap2_dflt, + .parent = &sys_ck, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_USBOTG_FCLK_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk hecc_ck = { + .name = "hecc_ck", + .ops = &clkops_omap2_dflt, + .parent = &sys_ck, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_HECC_VBUSP_CLK_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk vpfe_ick = { + .name = "vpfe_ick", + .ops = &clkops_omap2_dflt, + .parent = &core_l3_ick, + .clkdm_name = "core_l3_clkdm", + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_VPFE_VBUSP_CLK_SHIFT, + .recalc = &followparent_recalc, +}; + +static struct clk vpfe_fck = { + .name = "vpfe_fck", + .ops = &clkops_omap2_dflt, + .clkdm_name = "core_l3_clkdm", + .rate = 27000000, + .enable_reg = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL), + .enable_bit = AM35XX_VPFE_FCLK_SHIFT, + .recalc = &omap2_clksel_recalc, +}; + +/* + * The UART1/2 functional clock acts as the functional + * clock for UART4. No separate fclk control available. + */ +static struct clk uart4_ick = { + .name = "uart4_ick", + .ops = &clkops_omap2_dflt_wait, + .parent = &core_l4_ick, + .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), + .enable_bit = AM35XX_EN_UART4_SHIFT, + .clkdm_name = "core_l4_clkdm", + .recalc = &followparent_recalc, +}; + /* * clkdev @@ -3209,6 +3294,14 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_3XXX), CLK(NULL, "gpt12_fck", &gpt12_fck, CK_3XXX), CLK(NULL, "wdt1_fck", &wdt1_fck, CK_3XXX), + CLK("davinci_emac", "ick", &emac_ick, CK_AM35XX), + CLK("davinci_emac", "fck", &emac_fck, CK_AM35XX), + CLK("musb_hdrc", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), + CLK("musb_hdrc", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), + CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), + CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), + CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), + CLK(NULL, "uart4_ick", &uart4_ick, CK_AM35XX), }; diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 6923deb..39caf48 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -168,6 +168,12 @@ #define OMAP3430_EN_SDRC (1 << 1) #define OMAP3430_EN_SDRC_SHIFT 1 +/* + * On AM35XX MSPro is replaced by another UART (UART4) + */ +#define AM35XX_EN_UART4 (1 << 23) +#define AM35XX_EN_UART4_SHIFT 23 + /* CM_ICLKEN2_CORE */ #define OMAP3430_EN_PKA (1 << 4) #define OMAP3430_EN_PKA_SHIFT 4