From patchwork Mon Jan 11 06:06:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Hiremath X-Patchwork-Id: 72098 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0B66aL5001295 for ; Mon, 11 Jan 2010 06:06:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751475Ab0AKGGb (ORCPT ); Mon, 11 Jan 2010 01:06:31 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751456Ab0AKGG3 (ORCPT ); Mon, 11 Jan 2010 01:06:29 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:50789 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348Ab0AKGG2 (ORCPT ); Mon, 11 Jan 2010 01:06:28 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o0B66OvF000859 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 11 Jan 2010 00:06:26 -0600 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o0B66Lv6017787; Mon, 11 Jan 2010 11:36:23 +0530 (IST) From: hvaibhav@ti.com To: linux-omap@vger.kernel.org Cc: tony@atomide.com, khilman@deeprootsystems.com, Vaibhav Hiremath Subject: [PATCH 2/3-V1] AM35xx: Add AM35xx intr_clr & sw_rst cntrl reg bit defination Date: Mon, 11 Jan 2010 11:36:20 +0530 Message-Id: <1263189981-717-3-git-send-email-hvaibhav@ti.com> X-Mailer: git-send-email 1.6.2.4 In-Reply-To: References: Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h index 61e7b8a..efdf9e6 100644 --- a/arch/arm/plat-omap/include/plat/control.h +++ b/arch/arm/plat-omap/include/plat/control.h @@ -274,6 +274,23 @@ #define AM35XX_CPGMAC_FCLK_SHIFT 9 #define AM35XX_VPFE_FCLK_SHIFT 10 +/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ +#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) +#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) +#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) +#define AM35XX_CPGMAC_C0_TX_PULSE_CLR BIT(3) +#define AM35XX_USBOTGSS_INT_CLR BIT(4) +#define AM35XX_VPFE_CCDC_VD0_INT_CLR BIT(5) +#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) +#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) + +/*AM35XX CONTROL_IP_SW_RESET bits*/ +#define AM35XX_USBOTGSS_SW_RST BIT(0) +#define AM35XX_CPGMACSS_SW_RST BIT(1) +#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) +#define AM35XX_HECC_SW_RST BIT(3) +#define AM35XX_VPFE_PCLK_SW_RST BIT(4) + /* * CONTROL OMAP STATUS register to identify OMAP3 features */