From patchwork Fri Jan 15 12:46:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 73138 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.2) with ESMTP id o0FAtZpi023076 for ; Fri, 15 Jan 2010 10:55:35 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754445Ab0AOKzc (ORCPT ); Fri, 15 Jan 2010 05:55:32 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1755659Ab0AOKzc (ORCPT ); Fri, 15 Jan 2010 05:55:32 -0500 Received: from smtp.nokia.com ([192.100.122.230]:22094 "EHLO mgw-mx03.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750975Ab0AOKza (ORCPT ); Fri, 15 Jan 2010 05:55:30 -0500 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx03.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o0FAtCGt025527; Fri, 15 Jan 2010 12:55:27 +0200 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 15 Jan 2010 12:55:25 +0200 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 15 Jan 2010 12:55:25 +0200 Received: from localhost.localdomain (sokoban.nmp.nokia.com [172.22.215.13]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o0FAtE8P003555; Fri, 15 Jan 2010 12:55:24 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com Subject: [PATCHv3 6/6] OMAP3: CPUidle: Added peripheral pwrdm checks into bm check Date: Fri, 15 Jan 2010 14:46:57 +0200 Message-Id: <1263559617-663-7-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1263559617-663-6-git-send-email-tero.kristo@nokia.com> References: <> <1263559617-663-1-git-send-email-tero.kristo@nokia.com> <1263559617-663-2-git-send-email-tero.kristo@nokia.com> <1263559617-663-3-git-send-email-tero.kristo@nokia.com> <1263559617-663-4-git-send-email-tero.kristo@nokia.com> <1263559617-663-5-git-send-email-tero.kristo@nokia.com> <1263559617-663-6-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 15 Jan 2010 10:55:25.0692 (UTC) FILETIME=[3E26E3C0:01CA95D1] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 4a81ef1..dad64a9 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -58,7 +58,8 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd, *core_pd; +struct powerdomain *mpu_pd, *core_pd, *per_pd, *iva2_pd; +struct powerdomain *sgx_pd, *usb_pd, *cam_pd, *dss_pd; /* * The latencies/thresholds for various C states have @@ -92,6 +93,22 @@ static int omap3_idle_bm_check(void) } /** + * pwrdm_get_idle_state - Get the power state a pwrdm will enter during idle + * @pwrdm: powerdomain to check state for + * + * Checks if the powerdomain can enter idle or not, if yes, will return + * the programmed target state for the domain. Otherwise will indicate + * that the domain will stay on. + * Returns the power state the pwrdm will enter. + */ +static int pwrdm_get_idle_state(struct powerdomain *pwrdm) +{ + if (pwrdm_can_idle(pwrdm)) + return pwrdm_read_next_pwrst(pwrdm); + return PWRDM_POWER_ON; +} + +/** * omap3_enter_idle - Programs OMAP3 to enter the specified state * @dev: cpuidle device * @state: The target state to be programmed @@ -153,14 +170,94 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = state; - - if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { - BUG_ON(!dev->safe_state); - new_state = dev->safe_state; + u32 per_state = 0, saved_per_state = 0, cam_state, usb_state; + u32 iva2_state, sgx_state, dss_state, new_core_state; + struct omap3_processor_cx *cx; + int ret; + + if (state->flags & CPUIDLE_FLAG_CHECK_BM) { + if (omap3_idle_bm_check()) { + BUG_ON(!dev->safe_state); + new_state = dev->safe_state; + goto select_state; + } + cx = cpuidle_get_statedata(state); + new_core_state = cx->core_state; + + /* Check if CORE is active, if yes, fallback to inactive */ + if (!pwrdm_can_idle(core_pd)) + new_core_state = PWRDM_POWER_INACTIVE; + + /* + * Prevent idle completely if CAM is active. + * CAM does not have wakeup capability in OMAP3. + */ + cam_state = pwrdm_get_idle_state(cam_pd); + if (cam_state == PWRDM_POWER_ON) { + new_state = dev->safe_state; + goto select_state; + } + + /* + * Check if PER can idle or not. If we are not likely + * to idle, deny PER off. This prevents unnecessary + * context save/restore. + */ + saved_per_state = pwrdm_read_next_pwrst(per_pd); + if (pwrdm_can_idle(per_pd)) { + per_state = saved_per_state; + /* + * Prevent PER off if CORE is active as this + * would disable PER wakeups completely + */ + if (per_state == PWRDM_POWER_OFF && + new_core_state > PWRDM_POWER_RET) + per_state = PWRDM_POWER_RET; + + } else if (saved_per_state == PWRDM_POWER_OFF) + per_state = PWRDM_POWER_RET; + + /* + * If we are attempting CORE off, check if any other + * powerdomains are at retention or higher. CORE off causes + * chipwide reset which would reset these domains also. + */ + if (new_core_state == PWRDM_POWER_OFF) { + dss_state = pwrdm_get_idle_state(dss_pd); + iva2_state = pwrdm_get_idle_state(iva2_pd); + sgx_state = pwrdm_get_idle_state(sgx_pd); + usb_state = pwrdm_get_idle_state(usb_pd); + + if (cam_state > PWRDM_POWER_OFF || + dss_state > PWRDM_POWER_OFF || + iva2_state > PWRDM_POWER_OFF || + per_state > PWRDM_POWER_OFF || + sgx_state > PWRDM_POWER_OFF || + usb_state > PWRDM_POWER_OFF) + new_core_state = PWRDM_POWER_RET; + } + + /* Fallback to new target core state */ + while (cx->core_state > new_core_state) { + state--; + cx = cpuidle_get_statedata(state); + } + new_state = state; + + /* Are we changing PER target state? */ + if (per_state != saved_per_state) + pwrdm_set_next_pwrst(per_pd, per_state); } +select_state: dev->last_state = new_state; - return omap3_enter_idle(dev, new_state); + ret = omap3_enter_idle(dev, new_state); + + /* Restore potentially tampered PER state */ + if (per_state != saved_per_state) + pwrdm_set_next_pwrst(per_pd, saved_per_state); + + return ret; } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -224,7 +321,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].threshold; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_INACTIVE; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = @@ -322,6 +420,12 @@ int __init omap3_idle_init(void) mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); + per_pd = pwrdm_lookup("per_pwrdm"); + iva2_pd = pwrdm_lookup("iva2_pwrdm"); + sgx_pd = pwrdm_lookup("sgx_pwrdm"); + usb_pd = pwrdm_lookup("usbhost_pwrdm"); + cam_pd = pwrdm_lookup("cam_pwrdm"); + dss_pd = pwrdm_lookup("dss_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver);