@@ -105,14 +105,6 @@
CMM_DSPPA2PA = 4, /* DSP Pa to GPP Pa */
} ;
-/*
- * Used to "map" between device process virt addr and dsp addr.
- */
- enum CMM_KERNMAPTYPE {
- CMM_KERNVA2DSP = 0, /* Device process context to dsp address. */
- CMM_DSP2KERNVA = 1, /* Dsp address to device process context. */
- } ;
-
struct CMM_OBJECT;
struct CMM_XLATOROBJECT;
@@ -22,20 +22,5 @@
#define SYSC_IVA2BOOTADDR_OFFSET 0x400
#define SYSC_IVA2BOOTADDR_MASK 0xfffffc00
-
-/* The following represent the enumerated values for each bitfield */
-
-enum IPIIPI_SYSCONFIGAutoIdleE {
- IPIIPI_SYSCONFIGAutoIdleclkfree = 0x0000,
- IPIIPI_SYSCONFIGAutoIdleautoclkgate = 0x0001
-} ;
-
-enum IPIIPI_ENTRYElemSizeValueE {
- IPIIPI_ENTRYElemSizeValueElemSz8b = 0x0000,
- IPIIPI_ENTRYElemSizeValueElemSz16b = 0x0001,
- IPIIPI_ENTRYElemSizeValueElemSz32b = 0x0002,
- IPIIPI_ENTRYElemSizeValueReserved = 0x0003
-} ;
-
#endif /* _IPI_ACC_INT_H */
/* EOF */
@@ -270,21 +270,6 @@ static const struct BPWR_Clk_t BPWR_Clks[] = {
#define INTH_MASK_IT_REG_OFFSET 0x04 /* Mask Interrupt reg offset */
#define DSP_MAILBOX1_INT 10
-
-/*
- * INTH_InterruptKind_t
- * Identify the kind of interrupt: either FIQ/IRQ
- */
-enum INTH_InterruptKind_t {
- INTH_IRQ = 0,
- INTH_FIQ = 1
-} ;
-
-enum INTH_SensitiveEdge_t {
- FALLING_EDGE_SENSITIVE = 0,
- LOW_LEVEL_SENSITIVE = 1
-} ;
-
/*
* Bit definition of Interrupt Level Registers
*/