From patchwork Tue Feb 2 14:52:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 76370 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o12D3Kcc020153 for ; Tue, 2 Feb 2010 13:03:20 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755946Ab0BBNDT (ORCPT ); Tue, 2 Feb 2010 08:03:19 -0500 Received: from smtp.nokia.com ([192.100.122.233]:52309 "EHLO mgw-mx06.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755931Ab0BBNDS (ORCPT ); Tue, 2 Feb 2010 08:03:18 -0500 Received: from esebh106.NOE.Nokia.com (esebh106.ntc.nokia.com [172.21.138.213]) by mgw-mx06.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o12D2nq4028244 for ; Tue, 2 Feb 2010 15:03:15 +0200 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by esebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 15:03:08 +0200 Received: from mgw-sa02.ext.nokia.com ([147.243.1.48]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 15:03:08 +0200 Received: from localhost.localdomain (sokoban.nmp.nokia.com [172.22.215.13]) by mgw-sa02.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o12D2wJi029178 for ; Tue, 2 Feb 2010 15:03:06 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Subject: [PATCHv5 7/9] OMAP3: CPUidle: Added peripheral pwrdm checks into bm check Date: Tue, 2 Feb 2010 16:52:25 +0200 Message-Id: <1265122347-2233-8-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1265122347-2233-7-git-send-email-tero.kristo@nokia.com> References: <> <1265122347-2233-1-git-send-email-tero.kristo@nokia.com> <1265122347-2233-2-git-send-email-tero.kristo@nokia.com> <1265122347-2233-3-git-send-email-tero.kristo@nokia.com> <1265122347-2233-4-git-send-email-tero.kristo@nokia.com> <1265122347-2233-5-git-send-email-tero.kristo@nokia.com> <1265122347-2233-6-git-send-email-tero.kristo@nokia.com> <1265122347-2233-7-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 02 Feb 2010 13:03:08.0305 (UTC) FILETIME=[10DC5810:01CAA408] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 02 Feb 2010 13:03:20 +0000 (UTC) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 86f580b..38bd70c 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -58,7 +58,8 @@ struct omap3_processor_cx { struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES]; struct omap3_processor_cx current_cx_state; -struct powerdomain *mpu_pd, *core_pd; +static struct powerdomain *mpu_pd, *core_pd, *per_pd, *iva2_pd; +static struct powerdomain *sgx_pd, *usb_pd, *cam_pd, *dss_pd; /* * The latencies/thresholds for various C states have @@ -153,14 +154,94 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev, struct cpuidle_state *state) { struct cpuidle_state *new_state = state; - - if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) { - BUG_ON(!dev->safe_state); - new_state = dev->safe_state; + u32 per_state = 0, saved_per_state = 0, cam_state, usb_state; + u32 iva2_state, sgx_state, dss_state, new_core_state; + struct omap3_processor_cx *cx; + int ret; + + if (state->flags & CPUIDLE_FLAG_CHECK_BM) { + if (omap3_idle_bm_check()) { + BUG_ON(!dev->safe_state); + new_state = dev->safe_state; + goto select_state; + } + cx = cpuidle_get_statedata(state); + new_core_state = cx->core_state; + + /* Check if CORE is active, if yes, fallback to inactive */ + if (!pwrdm_can_idle(core_pd)) + new_core_state = PWRDM_POWER_INACTIVE; + + /* + * Prevent idle completely if CAM is active. + * CAM does not have wakeup capability in OMAP3. + */ + cam_state = pwrdm_read_pwrst(cam_pd); + if (cam_state == PWRDM_POWER_ON) { + new_state = dev->safe_state; + goto select_state; + } + + /* + * Check if PER can idle or not. If we are not likely + * to idle, deny PER off. This prevents unnecessary + * context save/restore. + */ + saved_per_state = omap3_pwrdm_read_next_pwrst(per_pd); + if (pwrdm_can_idle(per_pd)) { + per_state = saved_per_state; + /* + * Prevent PER off if CORE is active as this + * would disable PER wakeups completely + */ + if (per_state == PWRDM_POWER_OFF && + new_core_state > PWRDM_POWER_RET) + per_state = PWRDM_POWER_RET; + + } else if (saved_per_state == PWRDM_POWER_OFF) + per_state = PWRDM_POWER_RET; + + /* + * If we are attempting CORE off, check if any other + * powerdomains are at retention or higher. CORE off causes + * chipwide reset which would reset these domains also. + */ + if (new_core_state == PWRDM_POWER_OFF) { + dss_state = pwrdm_read_pwrst(dss_pd); + iva2_state = pwrdm_read_pwrst(iva2_pd); + sgx_state = pwrdm_read_pwrst(sgx_pd); + usb_state = pwrdm_read_pwrst(usb_pd); + + if (cam_state > PWRDM_POWER_OFF || + dss_state > PWRDM_POWER_OFF || + iva2_state > PWRDM_POWER_OFF || + per_state > PWRDM_POWER_OFF || + sgx_state > PWRDM_POWER_OFF || + usb_state > PWRDM_POWER_OFF) + new_core_state = PWRDM_POWER_RET; + } + + /* Fallback to new target core state */ + while (cx->core_state < new_core_state) { + state--; + cx = cpuidle_get_statedata(state); + } + new_state = state; + + /* Are we changing PER target state? */ + if (per_state != saved_per_state) + omap3_pwrdm_set_next_pwrst(per_pd, per_state); } +select_state: dev->last_state = new_state; - return omap3_enter_idle(dev, new_state); + ret = omap3_enter_idle(dev, new_state); + + /* Restore potentially tampered PER state */ + if (per_state != saved_per_state) + omap3_pwrdm_set_next_pwrst(per_pd, saved_per_state); + + return ret; } DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); @@ -224,7 +305,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].threshold; omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_INACTIVE; - omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; + omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | + CPUIDLE_FLAG_CHECK_BM; /* C3 . MPU CSWR + Core inactive */ omap3_power_states[OMAP3_STATE_C3].valid = @@ -322,6 +404,12 @@ int __init omap3_idle_init(void) mpu_pd = pwrdm_lookup("mpu_pwrdm"); core_pd = pwrdm_lookup("core_pwrdm"); + per_pd = pwrdm_lookup("per_pwrdm"); + iva2_pd = pwrdm_lookup("iva2_pwrdm"); + sgx_pd = pwrdm_lookup("sgx_pwrdm"); + usb_pd = pwrdm_lookup("usbhost_pwrdm"); + cam_pd = pwrdm_lookup("cam_pwrdm"); + dss_pd = pwrdm_lookup("dss_pwrdm"); omap_init_power_states(); cpuidle_register_driver(&omap3_idle_driver);