From patchwork Fri Feb 12 18:27:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 78914 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o1CGdjvR008736 for ; Fri, 12 Feb 2010 16:39:45 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757216Ab0BLQjo (ORCPT ); Fri, 12 Feb 2010 11:39:44 -0500 Received: from smtp.nokia.com ([192.100.105.134]:64043 "EHLO mgw-mx09.nokia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757214Ab0BLQjn (ORCPT ); Fri, 12 Feb 2010 11:39:43 -0500 Received: from vaebh106.NOE.Nokia.com (vaebh106.europe.nokia.com [10.160.244.32]) by mgw-mx09.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o1CGdMDc021705 for ; Fri, 12 Feb 2010 10:39:42 -0600 Received: from esebh102.NOE.Nokia.com ([172.21.138.183]) by vaebh106.NOE.Nokia.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Feb 2010 18:39:36 +0200 Received: from mgw-sa01.ext.nokia.com ([147.243.1.47]) by esebh102.NOE.Nokia.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 12 Feb 2010 18:39:36 +0200 Received: from localhost.localdomain (sokoban.nmp.nokia.com [172.22.215.13]) by mgw-sa01.ext.nokia.com (Switch-3.3.3/Switch-3.3.3) with ESMTP id o1CGdVLu021112 for ; Fri, 12 Feb 2010 18:39:35 +0200 From: Tero Kristo To: linux-omap@vger.kernel.org Subject: [PATCHv6 3/9] OMAP3: CPUidle: Fixed support for ON / INACTIVE states Date: Fri, 12 Feb 2010 20:27:39 +0200 Message-Id: <1265999265-4363-4-git-send-email-tero.kristo@nokia.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1265999265-4363-3-git-send-email-tero.kristo@nokia.com> References: <> <1265999265-4363-1-git-send-email-tero.kristo@nokia.com> <1265999265-4363-2-git-send-email-tero.kristo@nokia.com> <1265999265-4363-3-git-send-email-tero.kristo@nokia.com> X-OriginalArrivalTime: 12 Feb 2010 16:39:36.0744 (UTC) FILETIME=[F6B45A80:01CAAC01] X-Nokia-AV: Clean Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Fri, 12 Feb 2010 16:39:45 +0000 (UTC) diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 1cfa5a6..86f580b 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -91,20 +91,6 @@ static int omap3_idle_bm_check(void) return 0; } -static int _cpuidle_allow_idle(struct powerdomain *pwrdm, - struct clockdomain *clkdm) -{ - omap2_clkdm_allow_idle(clkdm); - return 0; -} - -static int _cpuidle_deny_idle(struct powerdomain *pwrdm, - struct clockdomain *clkdm) -{ - omap2_clkdm_deny_idle(clkdm); - return 0; -} - /** * omap3_enter_idle - Programs OMAP3 to enter the specified state * @dev: cpuidle device @@ -135,25 +121,15 @@ static int omap3_enter_idle(struct cpuidle_device *dev, core_state = PWRDM_POWER_RET; } - pwrdm_set_next_pwrst(mpu_pd, mpu_state); - pwrdm_set_next_pwrst(core_pd, core_state); + omap3_pwrdm_set_next_pwrst(mpu_pd, mpu_state); + omap3_pwrdm_set_next_pwrst(core_pd, core_state); if (omap_irq_pending() || need_resched()) goto return_sleep_time; - if (cx->type == OMAP3_STATE_C1) { - pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle); - pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle); - } - /* Execute ARM wfi */ omap_sram_idle(); - if (cx->type == OMAP3_STATE_C1) { - pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle); - pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle); - } - return_sleep_time: getnstimeofday(&ts_postidle); ts_idle = timespec_sub(ts_postidle, ts_preidle); @@ -246,8 +222,8 @@ void omap_init_power_states(void) cpuidle_params_table[OMAP3_STATE_C2].wake_latency; omap3_power_states[OMAP3_STATE_C2].threshold = cpuidle_params_table[OMAP3_STATE_C2].threshold; - omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; - omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_INACTIVE; + omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID; /* C3 . MPU CSWR + Core inactive */ @@ -261,7 +237,7 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C3].threshold = cpuidle_params_table[OMAP3_STATE_C3].threshold; omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; - omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM; @@ -276,7 +252,7 @@ void omap_init_power_states(void) omap3_power_states[OMAP3_STATE_C4].threshold = cpuidle_params_table[OMAP3_STATE_C4].threshold; omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; - omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; + omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_INACTIVE; omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_CHECK_BM;