@@ -385,6 +385,7 @@
#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
+#define INT_44XX_DSS_DSI1 (53 + IRQ_GIC_START)
#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
@@ -405,6 +406,7 @@
#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
+#define INT_44XX_DSS_DSI2 (84 + IRQ_GIC_START)
#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
@@ -442,7 +444,10 @@
#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
+#define INT_44XX_DUCATI_MMU_IRQ (100 + IRQ_GIC_START)
#define INT_44XX_MCPDM_IRQ (112 + IRQ_GIC_START)
+#define INT_4XX_DSS_HDMI (101 + IRQ_GIC_START)
+#define INT_44XX_KBD_CTL (120 + IRQ_GIC_START)
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
* 16 MPUIO lines */