@@ -38,6 +38,20 @@ config BRIDGE_DEBUG
help
Say Y to enable Bridge debugging capabilities
+config BRIDGE_CACHE_LINE_CHECK
+ bool "Check buffers to be 128 byte aligned"
+ depends on MPU_BRIDGE
+ default n
+ help
+ When the DSP processes data, the DSP cache controller loads 128-Byte
+ chunks (lines) from SDRAM and writes the data back in 128-Byte chunks.
+ If a DMM buffer does not start and end on a 128-Byte boundary, the data
+ preceding the start address (SA) from the 128-Byte boundary to the SA
+ and the data at addresses trailing the end address (EA) from the EA to
+ the next 128-Byte boundary will be loaded and written back as well.
+ This can lead to heap corruption. Say Y, to enforce the check for 128
+ byte alignment, buffers failing this check will be rejected.
+
comment "Bridge Notifications"
depends on MPU_BRIDGE
@@ -68,6 +68,8 @@
#define PWR_TIMEOUT 500 /* Sleep/wake timout in msec */
#define EXTEND "_EXT_END" /* Extmem end addr in DSP binary */
+#define DSP_CACHE_LINE 128
+
extern char *iva_img;
/* ----------------------------------- Globals */
@@ -1067,6 +1069,15 @@ dsp_status proc_map(void *hprocessor, void *pmpu_addr, u32 ul_size,
struct proc_object *p_proc_object = (struct proc_object *)hprocessor;
struct dmm_map_object *map_obj;
+#ifdef CONFIG_BRIDGE_CACHE_LINE_CHECK
+ if (!IS_ALIGNED((u32)pmpu_addr, DSP_CACHE_LINE) ||
+ !IS_ALIGNED(ul_size, DSP_CACHE_LINE)) {
+ pr_err("%s: not aligned: 0x%x (%d)\n", __func__,
+ (u32)pmpu_addr, ul_size);
+ return -EFAULT;
+ }
+#endif
+
/* Calculate the page-aligned PA, VA and size */
va_align = PG_ALIGN_LOW((u32) req_addr, PG_SIZE4K);
pa_align = PG_ALIGN_LOW((u32) pmpu_addr, PG_SIZE4K);