@@ -490,7 +490,10 @@ bit 3 - MMU element size = 8bit (valid only for non mixed page entries)
bit 4 - MMU element size = 16bit (valid only for non mixed page entries)
bit 5 - MMU element size = 32bit (valid only for non mixed page entries)
bit 6 - MMU element size = 64bit (valid only for non mixed page entries)
- */
+
+bit 14 - Input (read only) buffer
+bit 15 - Output (writeable) buffer
+*/
/* Types of mapping attributes */
@@ -518,6 +521,8 @@ bit 6 - MMU element size = 64bit (valid only for non mixed page entries)
#define DSP_MAPDONOTLOCK 0x00000100
+#define DSP_MAP_DIR_MASK 0x3FFF
+
#define GEM_CACHE_LINE_SIZE 128
#define GEM_L1P_PREFETCH_SIZE 128
@@ -70,6 +70,12 @@
#define DSP_CACHE_LINE 128
+#define BUFMODE_MASK (3 << 14)
+
+/* Buffer modes from DSP perspective */
+#define RBUF 0x4000 /* Input buffer */
+#define WBUF 0x8000 /* Output Buffer */
+
extern char *iva_img;
/* ----------------------------------- Globals */
@@ -1070,11 +1076,13 @@ dsp_status proc_map(void *hprocessor, void *pmpu_addr, u32 ul_size,
struct dmm_map_object *map_obj;
#ifdef CONFIG_BRIDGE_CACHE_LINE_CHECK
- if (!IS_ALIGNED((u32)pmpu_addr, DSP_CACHE_LINE) ||
- !IS_ALIGNED(ul_size, DSP_CACHE_LINE)) {
- pr_err("%s: not aligned: 0x%x (%d)\n", __func__,
+ if ((ul_map_attr & BUFMODE_MASK) != RBUF) {
+ if (!IS_ALIGNED((u32)pmpu_addr, DSP_CACHE_LINE) ||
+ !IS_ALIGNED(ul_size, DSP_CACHE_LINE)) {
+ pr_err("%s: not aligned: 0x%x (%d)\n", __func__,
(u32)pmpu_addr, ul_size);
- return -EFAULT;
+ return -EFAULT;
+ }
}
#endif
@@ -1308,11 +1308,11 @@ static dsp_status bridge_brd_mem_map(struct wmd_dev_context *hDevContext,
if (ul_num_bytes == 0)
return DSP_EINVALIDARG;
- if (ul_map_attr != 0) {
+ if (ul_map_attr & DSP_MAP_DIR_MASK) {
attrs = ul_map_attr;
} else {
/* Assign default attributes */
- attrs = DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16;
+ attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
}
/* Take mapping properties */
if (attrs & DSP_MAPBIGENDIAN)