From patchwork Tue Apr 13 12:37:08 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripathy, Vishwanath" X-Patchwork-Id: 92166 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3DCcGN1011984 for ; Tue, 13 Apr 2010 12:38:16 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751694Ab0DMMiO (ORCPT ); Tue, 13 Apr 2010 08:38:14 -0400 Received: from arroyo.ext.ti.com ([192.94.94.40]:54047 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751655Ab0DMMiN (ORCPT ); Tue, 13 Apr 2010 08:38:13 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3DCcA4c010803 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Tue, 13 Apr 2010 07:38:12 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3DCc8Cu016289; Tue, 13 Apr 2010 18:08:09 +0530 (IST) From: Vishwanath BS To: linux-omap@vger.kernel.org Cc: Teerth Reddy , Vishwanath BS Subject: [PATCHV3] OMAP3: SDRC : Errata 1.176 Fix - Accesses to DDR stall in SDRC after a Warm-reset Date: Tue, 13 Apr 2010 18:07:08 +0530 Message-Id: <1271162228-21260-1-git-send-email-vishwanath.bs@ti.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Tue, 13 Apr 2010 12:38:16 +0000 (UTC) diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 9537f6f..ac731b2 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "clock.h" #include "clock2xxx.h" @@ -141,6 +142,8 @@ void omap_prcm_arch_reset(char mode, const char *cmd) omap2xxx_clk_prepare_for_reboot(); prcm_offs = WKUP_MOD; + prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, + OMAP2_RM_RSTCTRL); } else if (cpu_is_omap34xx()) { u32 l; @@ -152,14 +155,12 @@ void omap_prcm_arch_reset(char mode, const char *cmd) * cf. OMAP34xx TRM, Initialization / Software Booting * Configuration. */ omap_writel(l, OMAP343X_SCRATCHPAD + 4); + omap3_configure_core_dpll_warmreset(); } else if (cpu_is_omap44xx()) prcm_offs = OMAP4430_PRM_DEVICE_MOD; else WARN_ON(1); - if (cpu_is_omap24xx() | cpu_is_omap34xx()) - prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, - OMAP2_RM_RSTCTRL); if (cpu_is_omap44xx()) prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, OMAP4_RM_RSTCTRL); diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index de99ba2..1a1be4d --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -33,6 +33,8 @@ #include "sdrc.h" #include "cm.h" +#include "prcm-common.h" +#include "prm.h" .text @@ -68,6 +70,9 @@ /* CM_CLKSEL1_PLL bit settings */ #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b +/* PRM_RSTCTRL bit setting */ +#define EN_DPLL3_RESET 0x4 + /* * omap3_sram_configure_core_dpll - change DPLL3 M2 divider * @@ -313,3 +318,49 @@ core_m2_mask_val: ENTRY(omap3_sram_configure_core_dpll_sz) .word . - omap3_sram_configure_core_dpll + +/* +* omap3_sram_configure_core_dpll_warmreset +* Enable SDRC self refresh on idle request, put SDRC in idle, +* wait until SDRC goes to idle +* Enable DPLL3 reset bit in RM_RSTCTRL +*/ + +ENTRY(omap3_sram_configure_core_dpll_warmreset) + + bl sdram_in_selfrefresh1 + ldr r11, omap3_reset_cntrl + ldr r12, [r11] + orr r12, r12, #EN_DPLL3_RESET @ Enable DPLL3 reset bit + str r12, [r11] + +sdram_in_selfrefresh1: + ldr r11, omap3_sdrc_power1 @ read the SDRC_POWER register + ldr r12, [r11] @ read the contents of SDRC_POWER + mov r9, r12 @ keep a copy of SDRC_POWER bits + orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle + str r12, [r11] @ write back to SDRC_POWER register + ldr r12, [r11] @ posted-write barrier for SDRC + ldr r11, omap3_cm_iclken1_core1 @ read the CM_ICLKEN1_CORE reg + ldr r12, [r11] + bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC + str r12, [r11] +wait_sdrc_idle2: + ldr r11, omap3_cm_idlest1_core1 + ldr r12, [r11] + and r12, r12, #ST_SDRC_MASK @ check for SDRC idle + cmp r12, #ST_SDRC_MASK + bne wait_sdrc_idle2 + bx lr + +omap3_reset_cntrl: + .word OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL) +omap3_sdrc_power1: + .word OMAP34XX_SDRC_REGADDR(SDRC_POWER) +omap3_cm_idlest1_core1: + .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST) +omap3_cm_iclken1_core1: + .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1) + +ENTRY(omap3_sram_configure_core_dpll_warmreset_sz) + .word . - omap3_sram_configure_core_dpll_warmreset diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h index 16a1b45..a6b1b11 --- a/arch/arm/plat-omap/include/plat/sram.h +++ b/arch/arm/plat-omap/include/plat/sram.h @@ -27,6 +27,9 @@ extern u32 omap3_configure_core_dpll( u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0, u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1, u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); + +extern void omap3_configure_core_dpll_warmreset(void); + extern void omap3_sram_restore_context(void); /* Do not use these */ @@ -69,6 +72,10 @@ extern u32 omap3_sram_configure_core_dpll( u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1); extern unsigned long omap3_sram_configure_core_dpll_sz; +extern void omap3_sram_configure_core_dpll_warmreset(void); + +extern unsigned long omap3_sram_configure_core_dpll_warmreset_sz; + #ifdef CONFIG_PM extern void omap_push_sram_idle(void); #else diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 51f4dfb..ecf1d6b --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -410,6 +410,18 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc, sdrc_actim_ctrl_b_1, sdrc_mr_1); } +/* Function for SDRC config for warm reset */ +static void (*_omap3_sram_configure_core_dpll_warmreset)(void); + +void omap3_configure_core_dpll_warmreset() +{ + if (WARN_ON(!_omap3_sram_configure_core_dpll_warmreset)) + return; + local_irq_disable(); + local_fiq_disable(); + _omap3_sram_configure_core_dpll_warmreset(); +} + #ifdef CONFIG_PM void omap3_sram_restore_context(void) { @@ -417,7 +429,10 @@ void omap3_sram_restore_context(void) _omap3_sram_configure_core_dpll = omap_sram_push(omap3_sram_configure_core_dpll, - omap3_sram_configure_core_dpll_sz); + omap3_sram_configure_core_dpll_sz); + _omap3_sram_configure_core_dpll_warmreset = + omap_sram_push(omap3_sram_configure_core_dpll_warmreset, + omap3_sram_configure_core_dpll_warmreset_sz); omap_push_sram_idle(); } #endif /* CONFIG_PM */ @@ -427,6 +442,10 @@ int __init omap34xx_sram_init(void) _omap3_sram_configure_core_dpll = omap_sram_push(omap3_sram_configure_core_dpll, omap3_sram_configure_core_dpll_sz); + + _omap3_sram_configure_core_dpll_warmreset = + omap_sram_push(omap3_sram_configure_core_dpll_warmreset, + omap3_sram_configure_core_dpll_warmreset_sz); omap_push_sram_idle(); return 0; }