From patchwork Wed Apr 28 01:29:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: omar ramirez X-Patchwork-Id: 95562 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3S1OtjT007834 for ; Wed, 28 Apr 2010 01:24:56 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754996Ab0D1BYv (ORCPT ); Tue, 27 Apr 2010 21:24:51 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:41676 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753274Ab0D1BYa (ORCPT ); Tue, 27 Apr 2010 21:24:30 -0400 Received: from dlep36.itg.ti.com ([157.170.170.91]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3S1OSAc001673 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 27 Apr 2010 20:24:28 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep36.itg.ti.com (8.13.8/8.13.8) with ESMTP id o3S1ORJ1028009; Tue, 27 Apr 2010 20:24:27 -0500 (CDT) Received: from Matrix (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o3S1ORZ04424; Tue, 27 Apr 2010 20:24:27 -0500 (CDT) Received: by Matrix (Postfix, from userid 1003) id 5A2341663D3; Tue, 27 Apr 2010 20:29:28 -0500 (CDT) From: Omar Ramirez Luna To: linux-omap Cc: Ameya Palande , Hiroshi Doyu , Felipe Contreras , Nishanth Menon , Omar Ramirez Luna Subject: [PATCH v2] DSPBRIDGE: function to get the type of clock requested by dsp Date: Tue, 27 Apr 2010 20:29:17 -0500 Message-Id: <1272418167-12630-10-git-send-email-omar.ramirez@ti.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1272418167-12630-9-git-send-email-omar.ramirez@ti.com> References: <1272418167-12630-1-git-send-email-omar.ramirez@ti.com> <1272418167-12630-2-git-send-email-omar.ramirez@ti.com> <1272418167-12630-3-git-send-email-omar.ramirez@ti.com> <1272418167-12630-4-git-send-email-omar.ramirez@ti.com> <1272418167-12630-5-git-send-email-omar.ramirez@ti.com> <1272418167-12630-6-git-send-email-omar.ramirez@ti.com> <1272418167-12630-7-git-send-email-omar.ramirez@ti.com> <1272418167-12630-8-git-send-email-omar.ramirez@ti.com> <1272418167-12630-9-git-send-email-omar.ramirez@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Apr 2010 01:24:56 +0000 (UTC) diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c index e35b929..d5c3d4e 100644 --- a/drivers/dsp/bridge/services/clk.c +++ b/drivers/dsp/bridge/services/clk.c @@ -40,6 +40,13 @@ #define SSI_SIDLE_SMARTIDLE (2 << 3) #define SSI_MIDLE_NOIDLE (1 << 12) +/* Clk types requested by the dsp */ +#define IVA2_CLK 0 +#define GPT_CLK 1 +#define WDT_CLK 2 +#define MCBSP_CLK 3 +#define SSI_CLK 4 + struct dsp_clk_t { struct clk *clk_handle; const char *clk_name; @@ -76,6 +83,26 @@ static struct dsp_clk_t dsp_clks[] = { {NULL, ""} }; +static s8 get_clk_type(u8 id) +{ + s8 type; + + if (id == DSP_CLK_IVA2_CK) + type = IVA2_CLK; + else if (id <= DSP_CLK_GPT8_ICK) + type = GPT_CLK; + else if (id <= DSP_CLK_WDT3_ICK) + type = WDT_CLK; + else if (id <= DSP_CLK_MCBSP5_ICK) + type = MCBSP_CLK; + else if (id < DSP_CLK_SSI_ICK) + type = SSI_CLK; + else + type = -1; + + return type; +} + /* * ======== dsp_clk_exit ======== * Purpose: @@ -141,23 +168,33 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id) dsp_status status = DSP_SOK; struct clk *clk_handle; - DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED); + switch (get_clk_type(clk_id)) { + case IVA2_CLK: + case GPT_CLK: + case MCBSP_CLK: + case WDT_CLK: + case SSI_CLK: + clk_handle = dsp_clks[clk_id].clk_handle; + if (clk_enable(clk_handle)) { + pr_err("dsp_clk_enable: failed to Enable CLK %s, " + "CLK dev id = %d\n", dsp_clks[clk_id].clk_name, + dsp_clks[clk_id].id); + status = -EPERM; + } - clk_handle = dsp_clks[clk_id].clk_handle; - if (clk_enable(clk_handle)) { - pr_err("dsp_clk_enable: failed to Enable CLK %s, " - "CLK dev id = %d\n", - dsp_clks[clk_id].clk_name, - dsp_clks[clk_id].id); - status = -EPERM; + /* + * The SSI module need to configured not to have the Forced + * idle for master interface. If it is set to forced idle, + * the SSI module is transitioning to standby thereby causing + * the client in the DSP hang waiting for the SSI module to + * be active after enabling the clocks + */ + if (clk_id == DSP_CLK_SSI_ICK) + ssi_clk_prepare(true); + break; + default: + dev_err(bridge, "Invalid clock id for enable\n"); } - /* The SSI module need to configured not to have the Forced idle for - * master interface. If it is set to forced idle, the SSI module is - * transitioning to standby thereby causing the client in the DSP hang - * waiting for the SSI module to be active after enabling the clocks - */ - if (clk_id == DSP_CLK_SSI_FCK) - ssi_clk_prepare(true); return status; } @@ -175,12 +212,22 @@ dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id) DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED); - clk_handle = dsp_clks[clk_id].clk_handle; - - if (clk_id == DSP_CLK_SSI_ICK) - ssi_clk_prepare(false); - - clk_disable(clk_handle); + switch (get_clk_type(clk_id)) { + case IVA2_CLK: + case GPT_CLK: + case MCBSP_CLK: + case WDT_CLK: + case SSI_CLK: + clk_handle = dsp_clks[clk_id].clk_handle; + + if (clk_id == DSP_CLK_SSI_ICK) + ssi_clk_prepare(false); + + clk_disable(clk_handle); + break; + default: + dev_err(bridge, "Invalid clock id for disable\n"); + } return status; }