From patchwork Wed Apr 28 15:29:44 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: omar ramirez X-Patchwork-Id: 95691 X-Patchwork-Delegate: omar.ramirez@ti.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o3SFOwEq018218 for ; Wed, 28 Apr 2010 15:24:58 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754979Ab0D1PY5 (ORCPT ); Wed, 28 Apr 2010 11:24:57 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:53592 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753060Ab0D1PY4 (ORCPT ); Wed, 28 Apr 2010 11:24:56 -0400 Received: from dlep35.itg.ti.com ([157.170.170.118]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o3SFOsCL020293 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 28 Apr 2010 10:24:54 -0500 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep35.itg.ti.com (8.13.7/8.13.7) with ESMTP id o3SFOs7W013828; Wed, 28 Apr 2010 10:24:54 -0500 (CDT) Received: from Matrix (matrix.am.dhcp.ti.com [128.247.75.166]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id o3SFOrZ24945; Wed, 28 Apr 2010 10:24:53 -0500 (CDT) Received: by Matrix (Postfix, from userid 1003) id EE89B1663D0; Wed, 28 Apr 2010 10:29:57 -0500 (CDT) From: Omar Ramirez Luna To: linux-omap Cc: Ameya Palande , Hiroshi Doyu , Felipe Contreras , Nishanth Menon , Omar Ramirez Luna Subject: [PATCH v2 06/19] DSPBRIDGE: remove function clk_set32k_hz Date: Wed, 28 Apr 2010 10:29:44 -0500 Message-Id: <1272468597-6748-7-git-send-email-omar.ramirez@ti.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1272468597-6748-6-git-send-email-omar.ramirez@ti.com> References: <1272468597-6748-1-git-send-email-omar.ramirez@ti.com> <1272468597-6748-2-git-send-email-omar.ramirez@ti.com> <1272468597-6748-3-git-send-email-omar.ramirez@ti.com> <1272468597-6748-4-git-send-email-omar.ramirez@ti.com> <1272468597-6748-5-git-send-email-omar.ramirez@ti.com> <1272468597-6748-6-git-send-email-omar.ramirez@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Wed, 28 Apr 2010 15:24:58 +0000 (UTC) diff --git a/arch/arm/plat-omap/include/dspbridge/clk.h b/arch/arm/plat-omap/include/dspbridge/clk.h index 2a43aab..5f7a925 100644 --- a/arch/arm/plat-omap/include/dspbridge/clk.h +++ b/arch/arm/plat-omap/include/dspbridge/clk.h @@ -45,7 +45,6 @@ enum dsp_clk_id { DSP_CLK_MCBSP5_ICK, DSP_CLK_SSI_FCK, DSP_CLK_SSI_ICK, - DSP_CLK_SYS32K_CK, DSP_CLK_NOT_DEFINED }; @@ -115,18 +114,7 @@ extern dsp_status dsp_clk_disable(IN enum dsp_clk_id clk_id); */ extern dsp_status dsp_clk_get_rate(IN enum dsp_clk_id clk_id, u32 *speedMhz); -/* - * ======== clk_set32k_hz ======== - * Purpose: - * Set the requested clock to 32KHz. - * Parameters: - * Returns: - * DSP_SOK: Success. - * -EPERM: Error occured while setting the clock parent to 32KHz. - * Requires: - * Ensures: - */ -extern dsp_status clk_set32k_hz(IN enum dsp_clk_id clk_id); + extern void ssi_clk_prepare(bool FLAG); /* diff --git a/drivers/dsp/bridge/services/clk.c b/drivers/dsp/bridge/services/clk.c index 23d4346..b4f5709 100644 --- a/drivers/dsp/bridge/services/clk.c +++ b/drivers/dsp/bridge/services/clk.c @@ -75,7 +75,6 @@ static struct dsp_clk_t dsp_clks[] = { {NULL, "mcbsp_ick", 5}, {NULL, "ssi_ssr_sst_fck", -1}, {NULL, "ssi_ick", -1}, - {NULL, "omap_32k_fck", -1}, {NULL, ""} }; @@ -171,31 +170,6 @@ dsp_status dsp_clk_enable(IN enum dsp_clk_id clk_id) } /* - * ======== clk_set32k_hz ======== - * Purpose: - * To Set parent of a clock to 32KHz. - */ - -dsp_status clk_set32k_hz(IN enum dsp_clk_id clk_id) -{ - dsp_status status = DSP_SOK; - struct clk *clk_handle; - struct clk *clk_parent; - clk_parent = dsp_clks[DSP_CLK_SYS32K_CK].clk_handle; - - DBC_REQUIRE(clk_id < DSP_CLK_NOT_DEFINED); - - clk_handle = dsp_clks[clk_id].clk_handle; - if (!(clk_set_parent(clk_handle, clk_parent) == 0x0)) { - pr_err("%s: failed for %s, dev id = %d\n", __func__, - dsp_clks[clk_id].clk_name, - dsp_clks[clk_id].id); - status = -EPERM; - } - return status; -} - -/* * ======== dsp_clk_disable ======== * Purpose: * Disable the clock. diff --git a/drivers/dsp/bridge/wmd/tiomap3430.c b/drivers/dsp/bridge/wmd/tiomap3430.c index 896941c..52ec3bc 100644 --- a/drivers/dsp/bridge/wmd/tiomap3430.c +++ b/drivers/dsp/bridge/wmd/tiomap3430.c @@ -543,13 +543,6 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext, } } - if (clk_id_index < MBX_PM_MAX_RESOURCES) { - status = - clk_set32k_hz(bpwr_clks - [clk_id_index].fun_clk); - } else { - status = -EPERM; - } clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | ul_load_monitor_timer; @@ -578,14 +571,6 @@ static dsp_status bridge_brd_start(struct wmd_dev_context *hDevContext, } } - if (clk_id_index < MBX_PM_MAX_RESOURCES) { - status = - clk_set32k_hz(bpwr_clks - [clk_id_index].fun_clk); - } else { - status = -EPERM; - } - clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) | ul_bios_gp_timer;