From patchwork Mon May 3 23:26:15 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 96632 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.3/8.14.3) with ESMTP id o43NQbvn005241 for ; Mon, 3 May 2010 23:26:37 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759798Ab0ECX0g (ORCPT ); Mon, 3 May 2010 19:26:36 -0400 Received: from mail-yx0-f171.google.com ([209.85.210.171]:55473 "EHLO mail-yx0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757180Ab0ECX0f (ORCPT ); Mon, 3 May 2010 19:26:35 -0400 Received: by yxe1 with SMTP id 1so668871yxe.33 for ; Mon, 03 May 2010 16:26:34 -0700 (PDT) Received: by 10.150.132.17 with SMTP id f17mr10478246ybd.286.1272929192169; Mon, 03 May 2010 16:26:32 -0700 (PDT) Received: from localhost (deeprootsystems.com [216.254.16.51]) by mx.google.com with ESMTPS id 20sm4690504iwn.13.2010.05.03.16.26.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 03 May 2010 16:26:31 -0700 (PDT) From: Kevin Hilman To: linux-omap@vger.kernel.org Subject: [PATCH 4/6] OMAP3: GPIO: disable GPIO debounce clocks on idle Date: Mon, 3 May 2010 16:26:15 -0700 Message-Id: <1272929177-22685-5-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.7.0.2 In-Reply-To: <1272929177-22685-1-git-send-email-khilman@deeprootsystems.com> References: <1272929177-22685-1-git-send-email-khilman@deeprootsystems.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Mon, 03 May 2010 23:26:37 +0000 (UTC) diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 48670ae..98465cd 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -196,6 +196,7 @@ struct gpio_bank { struct gpio_chip chip; struct clk *dbck; u32 mod_usage; + u32 dbck_enable_mask; }; #define METHOD_MPUIO 0 @@ -647,6 +648,7 @@ void omap_set_gpio_debounce(int gpio, int enable) goto done; if (cpu_is_omap34xx() || cpu_is_omap44xx()) { + bank->dbck_enable_mask = val; if (enable) clk_enable(bank->dbck); else @@ -2054,6 +2056,9 @@ void omap2_gpio_prepare_for_idle(int power_state) struct gpio_bank *bank = &gpio_bank[i]; u32 l1, l2; + if (bank->dbck_enable_mask) + clk_disable(bank->dbck); + if (power_state > PWRDM_POWER_OFF) continue; @@ -2118,6 +2123,9 @@ void omap2_gpio_resume_after_idle(void) struct gpio_bank *bank = &gpio_bank[i]; u32 l, gen, gen0, gen1; + if (bank->dbck_enable_mask) + clk_enable(bank->dbck); + if (!workaround_enabled) continue;