From patchwork Sat Aug 14 15:36:19 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 119553 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter.kernel.org (8.14.4/8.14.3) with ESMTP id o7E4aP1H006415 for ; Sat, 14 Aug 2010 04:37:06 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932460Ab0HNEhG (ORCPT ); Sat, 14 Aug 2010 00:37:06 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:45237 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751100Ab0HNEhE (ORCPT ); Sat, 14 Aug 2010 00:37:04 -0400 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id o7E4b0if010683 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 13 Aug 2010 23:37:02 -0500 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id o7E4axm5028510; Sat, 14 Aug 2010 10:06:59 +0530 (IST) From: Tarun Kanti DebBarma To: linux-omap@vger.kernel.org Cc: Partha Basak , Santosh Shilimkar , Thara Gopinath , Tarun Kanti DebBarma , Paul Walmsley , Kevin Hilman , Tony Lindgren Subject: [PATCHv2 8/13] dmtimer: OMAP: multi-platform register access support Date: Sat, 14 Aug 2010 21:06:19 +0530 Message-Id: <1281800179-15085-1-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter.kernel.org [140.211.167.41]); Sat, 14 Aug 2010 04:37:07 +0000 (UTC) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index 14a20e0..24ca283 100755 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -154,6 +154,7 @@ struct omap_dm_timer { unsigned long fclk_rate; int irq; void __iomem *io_base; + u32 *regs; unsigned reserved:1; unsigned enabled:1; unsigned posted:1; @@ -174,13 +175,14 @@ static DEFINE_SPINLOCK(dm_timer_lock); * pending bit must be checked. Otherwise a read of a non completed write * will produce an error. **/ -static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) +static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) { if (timer->posted) - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) - & (reg >> WPSHIFT)) + while (readl(timer->io_base + \ + ((timer->regs[OMAP_TIMER_WRITE_PEND_REG]) & 0xff)) + & (timer->regs[reg] >> WPSHIFT)) cpu_relax(); - return readl(timer->io_base + (reg & 0xff)); + return readl(timer->io_base + (timer->regs[reg] & 0xff)); } /** @@ -193,25 +195,38 @@ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) * pending bit must be checked. Otherwise a write on a register which has a * pending write will be lost. **/ -static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, +static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value) { if (timer->posted) - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) - & (reg >> WPSHIFT)) + while (readl(timer->io_base + \ + ((timer->regs[OMAP_TIMER_WRITE_PEND_REG]) & 0xff)) + & (timer->regs[reg] >> WPSHIFT)) cpu_relax(); - writel(value, timer->io_base + (reg & 0xff)); + writel(value, timer->io_base + (timer->regs[reg] & 0xff)); } static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) { int c; + u32 reg; + int reset_is_active; + struct omap_dmtimer_platform_data *pdata = \ + timer->pdev->dev.platform_data; + + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) { + reg = OMAP_TIMER_OCP_CFG_REG; + reset_is_active = 1; + } else { + reg = OMAP_TIMER_SYS_STAT_REG; + reset_is_active = 0; + } c = 0; - while (!(omap_dm_timer_read_reg(timer, OMAP_TIMER_SYS_STAT_REG) & 1)) { + while (omap_dm_timer_read_reg(timer, reg) == reset_is_active) { c++; if (c > 100000) { - printk(KERN_ERR "Timer failed to reset\n"); + printk(KERN_ERR "%s:Timer failed to reset\n", __func__); return; } } @@ -500,10 +515,17 @@ void omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, unsigned int value) { u32 l; + struct omap_dmtimer_platform_data *pdata = \ + timer->pdev->dev.platform_data; l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG); - l &= ~value; - omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, l); + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) { + l |= value; + omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_CLR_REG, value); + } else { + l &= ~value; + omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, l); + } omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); } EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable); @@ -624,6 +646,11 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_release_ioregion; } + if (pdata->timer_ip_type == OMAP_TIMER_IP_VERSION_2) + timer->regs = (u32 *) omap4_reg_map; + else + timer->regs = (u32 *) reg_map; + timer->io_base = ioremap(mem->start, resource_size(mem)); if (!timer->io_base) { dev_err(&pdev->dev, "%s: ioremap failed\n", __func__);