From patchwork Fri Nov 19 01:54:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 338031 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oAJ1t5eS025093 for ; Fri, 19 Nov 2010 01:55:08 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760266Ab0KSBzE (ORCPT ); Thu, 18 Nov 2010 20:55:04 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:51909 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756150Ab0KSBzC (ORCPT ); Thu, 18 Nov 2010 20:55:02 -0500 Received: from dlep34.itg.ti.com ([157.170.170.115]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id oAJ1t0Bl006751 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 18 Nov 2010 19:55:00 -0600 Received: from legion.dal.design.ti.com (localhost [127.0.0.1]) by dlep34.itg.ti.com (8.13.7/8.13.7) with ESMTP id oAJ1sxFb016900; Thu, 18 Nov 2010 19:55:00 -0600 (CST) Received: from senorita (senorita.am.dhcp.ti.com [128.247.74.250]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id oAJ1sxf12097; Thu, 18 Nov 2010 19:54:59 -0600 (CST) Received: by senorita (Postfix, from userid 1000) id 10106C2B1; Thu, 18 Nov 2010 19:54:58 -0600 (CST) From: Nishanth Menon To: linux-omap Cc: Kevin , Jean Pihet , Vishwanath Sripathy , Tony Subject: [PATCH 07/13] OMAP3: PM: allocate secure RAM context memory from low-mem Date: Thu, 18 Nov 2010 19:54:52 -0600 Message-Id: <1290131698-6194-8-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.6.3.3 In-Reply-To: <1290131698-6194-1-git-send-email-nm@ti.com> References: <1290131698-6194-1-git-send-email-nm@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 19 Nov 2010 01:55:08 +0000 (UTC) diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 40562dd..6098f81 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -41,6 +41,7 @@ #include #include #include "powerdomains.h" +#include "pm.h" #include #include "clockdomains.h" @@ -230,6 +231,13 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif +static void __init _omap_pm_reserve_sdram_memblock(void) +{ + if (cpu_is_omap34xx()) + omap3_pm_reserve_sdram_memblock(); + +} + static void __init _omap2_map_common_io(void) { /* Normally devicemaps_init() would flush caches and tlb after @@ -241,6 +249,9 @@ static void __init _omap2_map_common_io(void) omap2_check_revision(); omap_sram_init(); + + /* Allocate the secure SRAM storage after sram init and cpu detect */ + _omap_pm_reserve_sdram_memblock(); } #ifdef CONFIG_ARCH_OMAP2420 diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 39934ec..fcca056 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -114,11 +114,13 @@ struct omap3_secure_copy_data { #if defined(CONFIG_PM) extern int __init omap3_secure_copy_data_set(struct omap3_secure_copy_data *d); +extern void __init omap3_pm_reserve_sdram_memblock(void); #else static inline int omap3_secure_copy_data_set(struct omap3_secure_copy_data *d) { return -EINVAL; } +static inline void omap3_pm_reserve_sdram_memblock(void) { } #endif #endif diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index bbb1a40..7877f74 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -60,6 +61,8 @@ static struct omap3_secure_copy_data secure_copy_data = { .save_every_cycle = false, /* explicit for readability */ }; +#define OMAP3_SECURE_MAX_ALLOCATE_ADDRESS 0x8fffffff + struct power_state { struct powerdomain *pwrdm; u32 next_state; @@ -198,7 +201,7 @@ static void omap3_save_secure_ram_context(u32 target_mpu_state) */ pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); secure_ram_save_status = _omap_save_secure_sram((u32 *) - __pa(omap3_secure_ram_storage)); + (omap3_secure_ram_storage)); pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); if (!secure_copy_data.save_every_cycle) secure_ram_saved = 1; @@ -1065,14 +1068,6 @@ static int __init omap3_pm_init(void) omap3_idle_init(); clkdm_add_wkdep(neon_clkdm, mpu_clkdm); - if (omap_type() != OMAP2_DEVICE_TYPE_GP) { - omap3_secure_ram_storage = - kmalloc(secure_copy_data.size, GFP_KERNEL); - if (!omap3_secure_ram_storage) - printk(KERN_ERR "Memory allocation failed when" - "allocating for secure sram context\n"); - - } omap3_save_scratchpad_contents(); err1: @@ -1087,3 +1082,29 @@ err2: } late_initcall(omap3_pm_init); + +void __init omap3_pm_reserve_sdram_memblock(void) +{ + phys_addr_t size = secure_copy_data.size; + phys_addr_t paddr; + phys_addr_t max_addr = OMAP3_SECURE_MAX_ALLOCATE_ADDRESS; + + if (!size || !cpu_is_omap34xx() || omap_type() == OMAP2_DEVICE_TYPE_GP) + return; + + /* + * On OMAP3 Silicon, due to ROM Code limitation, we should + * not have the allocation beyond the first 256MB area. + * This limitation is true for both OMAP3430 and 3630 and + * all versions of the same. + */ + paddr = memblock_alloc_base(size, SZ_1M, max_addr); + + if (!paddr) { + pr_err("%s: failed to reserve %x bytes\n", + __func__, size); + return; + } + + omap3_secure_ram_storage = (void *)paddr; +}