From patchwork Thu Dec 9 23:33:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Cousson X-Patchwork-Id: 396892 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oB9NYd44003360 for ; Thu, 9 Dec 2010 23:34:40 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756464Ab0LIXej (ORCPT ); Thu, 9 Dec 2010 18:34:39 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:52348 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756315Ab0LIXei (ORCPT ); Thu, 9 Dec 2010 18:34:38 -0500 Received: from dlep33.itg.ti.com ([157.170.170.112]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id oB9NYVmg010966 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 9 Dec 2010 17:34:31 -0600 Received: from dlep26.itg.ti.com (localhost [127.0.0.1]) by dlep33.itg.ti.com (8.13.7/8.13.7) with ESMTP id oB9NYVuR002877; Thu, 9 Dec 2010 17:34:31 -0600 (CST) Received: from dlee74.ent.ti.com (localhost [127.0.0.1]) by dlep26.itg.ti.com (8.13.8/8.13.8) with ESMTP id oB9NYVDN012251; Thu, 9 Dec 2010 17:34:31 -0600 (CST) Received: from dlelxv22.itg.ti.com (172.17.1.197) by dlee74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 8.3.106.1; Thu, 9 Dec 2010 17:34:31 -0600 Received: from localhost.localdomain (lncpu04.tif.ti.com [137.167.102.15]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id oB9NYF7c020841; Thu, 9 Dec 2010 17:34:29 -0600 From: Benoit Cousson To: , CC: , , Benoit Cousson , Rajendra Nayak Subject: [PATCH 5/5] OMAP4: hwmod & clock data: Fix GPIO opt_clks and ocp_if iclk Date: Fri, 10 Dec 2010 00:33:35 +0100 Message-ID: <1291937615-18571-6-git-send-email-b-cousson@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1291937615-18571-1-git-send-email-b-cousson@ti.com> References: <1291937615-18571-1-git-send-email-b-cousson@ti.com> MIME-Version: 1.0 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Thu, 09 Dec 2010 23:34:40 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 1599836..c59a5a9 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -2856,17 +2856,17 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), - CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X), + CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), - CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X), + CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), - CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X), + CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), - CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X), + CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), - CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X), + CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), - CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X), + CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 102c76f..0ed9cdd 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -696,6 +696,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { .master = &omap44xx_l4_wkup_hwmod, .slave = &omap44xx_gpio1_hwmod, + .clk = "l4_wkup_clk_mux_ck", .addr = omap44xx_gpio1_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -707,7 +708,7 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = { }; static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { - { .role = "dbclk", .clk = "sys_32k_ck" }, + { .role = "dbclk", .clk = "gpio1_dbclk" }, }; static struct omap_hwmod omap44xx_gpio1_hwmod = { @@ -747,6 +748,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio2_hwmod, + .clk = "l4_div_ck", .addr = omap44xx_gpio2_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -758,12 +760,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = { }; static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { - { .role = "dbclk", .clk = "sys_32k_ck" }, + { .role = "dbclk", .clk = "gpio2_dbclk" }, }; static struct omap_hwmod omap44xx_gpio2_hwmod = { .name = "gpio2", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio2_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs), .main_clk = "gpio2_ick", @@ -798,6 +801,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio3_hwmod, + .clk = "l4_div_ck", .addr = omap44xx_gpio3_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -809,12 +813,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { }; static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { - { .role = "dbclk", .clk = "sys_32k_ck" }, + { .role = "dbclk", .clk = "gpio3_dbclk" }, }; static struct omap_hwmod omap44xx_gpio3_hwmod = { .name = "gpio3", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio3_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), .main_clk = "gpio3_ick", @@ -849,6 +854,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio4_hwmod, + .clk = "l4_div_ck", .addr = omap44xx_gpio4_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -860,12 +866,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = { }; static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { - { .role = "dbclk", .clk = "sys_32k_ck" }, + { .role = "dbclk", .clk = "gpio4_dbclk" }, }; static struct omap_hwmod omap44xx_gpio4_hwmod = { .name = "gpio4", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio4_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs), .main_clk = "gpio4_ick", @@ -900,6 +907,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio5_hwmod, + .clk = "l4_div_ck", .addr = omap44xx_gpio5_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -911,12 +919,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = { }; static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { - { .role = "dbclk", .clk = "sys_32k_ck" }, + { .role = "dbclk", .clk = "gpio5_dbclk" }, }; static struct omap_hwmod omap44xx_gpio5_hwmod = { .name = "gpio5", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio5_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), .main_clk = "gpio5_ick", @@ -951,6 +960,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { .master = &omap44xx_l4_per_hwmod, .slave = &omap44xx_gpio6_hwmod, + .clk = "l4_div_ck", .addr = omap44xx_gpio6_addrs, .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs), .user = OCP_USER_MPU | OCP_USER_SDMA, @@ -962,12 +972,13 @@ static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = { }; static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { - { .role = "dbclk", .clk = "sys_32k_ck" }, + { .role = "dbclk", .clk = "gpio6_dbclk" }, }; static struct omap_hwmod omap44xx_gpio6_hwmod = { .name = "gpio6", .class = &omap44xx_gpio_hwmod_class, + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, .mpu_irqs = omap44xx_gpio6_irqs, .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs), .main_clk = "gpio6_ick",