From patchwork Fri Dec 10 19:52:00 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 399382 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBAJs41C011820 for ; Fri, 10 Dec 2010 19:54:05 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756950Ab0LJTxc (ORCPT ); Fri, 10 Dec 2010 14:53:32 -0500 Received: from mail-wy0-f174.google.com ([74.125.82.174]:63486 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756066Ab0LJTxb (ORCPT ); Fri, 10 Dec 2010 14:53:31 -0500 Received: by wyb28 with SMTP id 28so3822510wyb.19 for ; Fri, 10 Dec 2010 11:53:29 -0800 (PST) Received: by 10.216.169.76 with SMTP id m54mr1438330wel.31.1292010809764; Fri, 10 Dec 2010 11:53:29 -0800 (PST) Received: from localhost.localdomain (147.70-245-81.adsl-dyn.isp.belgacom.be [81.245.70.147]) by mx.google.com with ESMTPS id m10sm2350391wbc.10.2010.12.10.11.53.28 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 10 Dec 2010 11:53:29 -0800 (PST) From: jean.pihet@newoldbits.com To: Ingo Molnar Cc: Thomas Renninger , linux-pm@lists.linux-foundation.org, Arjan van de Ven , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, Jean Pihet Subject: [PATCH 2/3] perf: add OMAP support for the new power events Date: Fri, 10 Dec 2010 20:52:00 +0100 Message-Id: <1292010721-17426-3-git-send-email-j-pihet@ti.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292010721-17426-1-git-send-email-j-pihet@ti.com> References: <1292010721-17426-1-git-send-email-j-pihet@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 10 Dec 2010 19:54:05 +0000 (UTC) diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0ec8a04..0ee0b0e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -506,8 +507,14 @@ static void omap3_pm_idle(void) if (omap_irq_pending() || need_resched()) goto out; + trace_power_start(POWER_CSTATE, 1, smp_processor_id()); + trace_cpu_idle(1, smp_processor_id()); + omap_sram_idle(); + trace_power_end(smp_processor_id()); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); + out: local_fiq_enable(); local_irq_enable(); diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 6527ec3..73cbe9a 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -23,6 +23,7 @@ #include #include #include +#include #include @@ -440,6 +441,8 @@ int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) pr_debug("powerdomain: setting next powerstate for %s to %0x\n", pwrdm->name, pwrst); + trace_power_domain_target(pwrdm->name, pwrst, smp_processor_id()); + prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), pwrdm->prcm_offs, pwrstctrl_reg_offs); diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index fc62fb5..7cbb09b 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c @@ -21,6 +21,7 @@ #include #include #include +#include #include @@ -43,8 +44,10 @@ int clk_enable(struct clk *clk) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_enable) + if (arch_clock->clk_enable) { + trace_clock_enable(clk->name, 1, smp_processor_id()); ret = arch_clock->clk_enable(clk); + } spin_unlock_irqrestore(&clockfw_lock, flags); return ret; @@ -66,8 +69,10 @@ void clk_disable(struct clk *clk) goto out; } - if (arch_clock->clk_disable) + if (arch_clock->clk_disable) { + trace_clock_disable(clk->name, 0, smp_processor_id()); arch_clock->clk_disable(clk); + } out: spin_unlock_irqrestore(&clockfw_lock, flags); @@ -120,8 +125,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate) return ret; spin_lock_irqsave(&clockfw_lock, flags); - if (arch_clock->clk_set_rate) + if (arch_clock->clk_set_rate) { + trace_clock_set_rate(clk->name, rate, smp_processor_id()); ret = arch_clock->clk_set_rate(clk, rate); + } if (ret == 0) { if (clk->recalc) clk->rate = clk->recalc(clk);