From patchwork Fri Dec 17 10:08:23 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 415171 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBHA8jYN028256 for ; Fri, 17 Dec 2010 10:08:48 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753328Ab0LQKIr (ORCPT ); Fri, 17 Dec 2010 05:08:47 -0500 Received: from mail-wy0-f174.google.com ([74.125.82.174]:35811 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753272Ab0LQKIq (ORCPT ); Fri, 17 Dec 2010 05:08:46 -0500 Received: by mail-wy0-f174.google.com with SMTP id 28so447876wyb.19 for ; Fri, 17 Dec 2010 02:08:45 -0800 (PST) Received: by 10.227.132.209 with SMTP id c17mr385967wbt.135.1292580525585; Fri, 17 Dec 2010 02:08:45 -0800 (PST) Received: from localhost.localdomain ([81.245.16.223]) by mx.google.com with ESMTPS id q18sm76619wbe.23.2010.12.17.02.08.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 17 Dec 2010 02:08:45 -0800 (PST) From: jean.pihet@newoldbits.com To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, linux-arm-kernel@lists.infradead.org, Jean Pihet Subject: [PATCH 4/7] OMAP3: re-organize the ASM sleep code Date: Fri, 17 Dec 2010 11:08:23 +0100 Message-Id: <1292580506-4421-5-git-send-email-j-pihet@ti.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292580506-4421-1-git-send-email-j-pihet@ti.com> References: <1292580506-4421-1-git-send-email-j-pihet@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Fri, 17 Dec 2010 10:08:49 +0000 (UTC) diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 8e9f38f..beeb682 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -79,6 +79,7 @@ ENTRY(get_restore_pointer) ldmfd sp!, {pc} @ restore regs and return ENTRY(get_restore_pointer_sz) .word . - get_restore_pointer + .text /* Function call to get the restore pointer for 3630 resume from OFF */ ENTRY(get_omap3630_restore_pointer) @@ -89,9 +90,18 @@ ENTRY(get_omap3630_restore_pointer_sz) .word . - get_omap3630_restore_pointer .text +/* Function call to get the restore pointer for ES3 to resume from OFF */ +ENTRY(get_es3_restore_pointer) + stmfd sp!, {lr} @ save registers on stack + adr r0, restore_es3 + ldmfd sp!, {pc} @ restore regs and return +ENTRY(get_es3_restore_pointer_sz) + .word . - get_es3_restore_pointer + + .text /* * L2 cache needs to be toggled for stable OFF mode functionality on 3630. - * This function sets up a fflag that will allow for this toggling to take + * This function sets up a flag that will allow for this toggling to take * place on 3630. Hopefully some version in the future maynot need this */ ENTRY(enable_omap3630_toggle_l2_on_restore) @@ -101,58 +111,6 @@ ENTRY(enable_omap3630_toggle_l2_on_restore) str r1, l2dis_3630 ldmfd sp!, {pc} @ restore regs and return - .text -/* Function call to get the restore pointer for for ES3 to resume from OFF */ -ENTRY(get_es3_restore_pointer) - stmfd sp!, {lr} @ save registers on stack - adr r0, restore_es3 - ldmfd sp!, {pc} @ restore regs and return -ENTRY(get_es3_restore_pointer_sz) - .word . - get_es3_restore_pointer - -ENTRY(es3_sdrc_fix) - ldr r4, sdrc_syscfg @ get config addr - ldr r5, [r4] @ get value - tst r5, #0x100 @ is part access blocked - it eq - biceq r5, r5, #0x100 @ clear bit if set - str r5, [r4] @ write back change - ldr r4, sdrc_mr_0 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_emr2_0 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_manual_0 @ get config addr - mov r5, #0x2 @ autorefresh command - str r5, [r4] @ kick off refreshes - ldr r4, sdrc_mr_1 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_emr2_1 @ get config addr - ldr r5, [r4] @ get value - str r5, [r4] @ write back change - ldr r4, sdrc_manual_1 @ get config addr - mov r5, #0x2 @ autorefresh command - str r5, [r4] @ kick off refreshes - bx lr -sdrc_syscfg: - .word SDRC_SYSCONFIG_P -sdrc_mr_0: - .word SDRC_MR_0_P -sdrc_emr2_0: - .word SDRC_EMR2_0_P -sdrc_manual_0: - .word SDRC_MANUAL_0_P -sdrc_mr_1: - .word SDRC_MR_1_P -sdrc_emr2_1: - .word SDRC_EMR2_1_P -sdrc_manual_1: - .word SDRC_MANUAL_1_P -ENTRY(es3_sdrc_fix_sz) - .word . - es3_sdrc_fix - /* Function to call rom code to save secure ram context */ ENTRY(save_secure_ram_context) stmfd sp!, {r1-r12, lr} @ save registers on stack @@ -577,6 +535,56 @@ skip_l2_inval: /* restore regs and return */ ldmfd sp!, {r0-r12, pc} + +/* + * Internal functions + */ + + .text +ENTRY(es3_sdrc_fix) + ldr r4, sdrc_syscfg @ get config addr + ldr r5, [r4] @ get value + tst r5, #0x100 @ is part access blocked + it eq + biceq r5, r5, #0x100 @ clear bit if set + str r5, [r4] @ write back change + ldr r4, sdrc_mr_0 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_emr2_0 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_manual_0 @ get config addr + mov r5, #0x2 @ autorefresh command + str r5, [r4] @ kick off refreshes + ldr r4, sdrc_mr_1 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_emr2_1 @ get config addr + ldr r5, [r4] @ get value + str r5, [r4] @ write back change + ldr r4, sdrc_manual_1 @ get config addr + mov r5, #0x2 @ autorefresh command + str r5, [r4] @ kick off refreshes + bx lr + +sdrc_syscfg: + .word SDRC_SYSCONFIG_P +sdrc_mr_0: + .word SDRC_MR_0_P +sdrc_emr2_0: + .word SDRC_EMR2_0_P +sdrc_manual_0: + .word SDRC_MANUAL_0_P +sdrc_mr_1: + .word SDRC_MR_1_P +sdrc_emr2_1: + .word SDRC_EMR2_1_P +sdrc_manual_1: + .word SDRC_MANUAL_1_P +ENTRY(es3_sdrc_fix_sz) + .word . - es3_sdrc_fix + /* Make sure SDRC accesses are ok */ wait_sdrc_ok: