From patchwork Sat Dec 18 15:44:43 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean Pihet X-Patchwork-Id: 418261 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBIFpH74005080 for ; Sat, 18 Dec 2010 15:51:17 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756694Ab0LRPvQ (ORCPT ); Sat, 18 Dec 2010 10:51:16 -0500 Received: from mail-ww0-f42.google.com ([74.125.82.42]:53962 "EHLO mail-ww0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756211Ab0LRPvP (ORCPT ); Sat, 18 Dec 2010 10:51:15 -0500 Received: by wwi17 with SMTP id 17so1496656wwi.1 for ; Sat, 18 Dec 2010 07:51:14 -0800 (PST) Received: by 10.216.62.143 with SMTP id y15mr2617290wec.55.1292687104756; Sat, 18 Dec 2010 07:45:04 -0800 (PST) Received: from localhost.localdomain (223.78-245-81.adsl-dyn.isp.belgacom.be [81.245.78.223]) by mx.google.com with ESMTPS id t11sm250385wes.41.2010.12.18.07.45.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 18 Dec 2010 07:45:03 -0800 (PST) From: jean.pihet@newoldbits.com To: linux-omap@vger.kernel.org Cc: khilman@deeprootsystems.com, linux-arm-kernel@lists.infradead.org, Jean Pihet , Vishwanath BS Subject: [PATCH 3/7] OMAP3: remove hardcoded values from the ASM sleep code Date: Sat, 18 Dec 2010 16:44:43 +0100 Message-Id: <1292687087-22983-4-git-send-email-j-pihet@ti.com> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1292687087-22983-1-git-send-email-j-pihet@ti.com> References: <1292687087-22983-1-git-send-email-j-pihet@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Sat, 18 Dec 2010 15:51:17 +0000 (UTC) diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index d7911c5..72efefb 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -274,6 +274,8 @@ #define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860) #define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910) #define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C +#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\ + OMAP343X_SCRATCHPAD + reg) /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index 406cd2a..8e9f38f 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -34,20 +34,27 @@ #include "sdrc.h" #include "control.h" -#define SDRC_SCRATCHPAD_SEM_V 0xfa00291c - -#define PM_PREPWSTST_CORE_P 0x48306AE8 +/* + * Registers access definitions + */ +#define SDRC_SCRATCHPAD_SEM_OFFS 0xc +#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\ + (SDRC_SCRATCHPAD_SEM_OFFS) +#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\ + OMAP3430_PM_PREPWSTST #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1) #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST) -#define SRAM_BASE_P 0x40200000 -#define CONTROL_STAT 0x480022F0 -#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE\ - + OMAP36XX_CONTROL_MEM_RTA_CTRL) -#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is - * available */ -#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE + OMAP343X_CONTROL_MEM_WKUP\ - + SCRATCHPAD_MEM_OFFS) +#define SRAM_BASE_P OMAP3_SRAM_PA +#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS +#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\ + OMAP36XX_CONTROL_MEM_RTA_CTRL) + +/* Move this as correct place is available */ +#define SCRATCHPAD_MEM_OFFS 0x310 +#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\ + OMAP343X_CONTROL_MEM_WKUP +\ + SCRATCHPAD_MEM_OFFS) #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER) #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG) #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)