From patchwork Wed Jan 19 14:14:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 489461 X-Patchwork-Delegate: paul@pwsan.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p0JEuJCq010815 for ; Wed, 19 Jan 2011 17:06:49 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754411Ab1ASOOi (ORCPT ); Wed, 19 Jan 2011 09:14:38 -0500 Received: from bear.ext.ti.com ([192.94.94.41]:49531 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754331Ab1ASOOg (ORCPT ); Wed, 19 Jan 2011 09:14:36 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id p0JEEUMV009234 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 19 Jan 2011 08:14:33 -0600 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p0JEERn9017804; Wed, 19 Jan 2011 19:44:28 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id p0JEERZM023718; Wed, 19 Jan 2011 19:44:27 +0530 Received: (from a0131687@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id p0JEER2f023716; Wed, 19 Jan 2011 19:44:27 +0530 From: Rajendra Nayak To: linux-omap@vger.kernel.org Cc: paul@pwsan.com, khilman@deeprootsystems.com, Rajendra Nayak Subject: [RFC 2/3] OMAP3: PM: Fix CLK_SRC mask for IVA2 and MPU on 3430ES2PLUS Date: Wed, 19 Jan 2011 19:44:25 +0530 Message-Id: <1295446466-23655-3-git-send-email-rnayak@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1295446466-23655-2-git-send-email-rnayak@ti.com> References: <1295446466-23655-1-git-send-email-rnayak@ti.com> <1295446466-23655-2-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 19 Jan 2011 17:07:05 +0000 (UTC) diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 9c87adb..c3a7ff5 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -53,10 +53,6 @@ * DPLL5 supplies other peripheral clocks (USBHOST, USIM). */ -/* Forward declarations for DPLL bypass clocks */ -static struct clk dpll1_fck; -static struct clk dpll2_fck; - /* PRM CLOCKS */ /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ @@ -275,7 +271,7 @@ static struct dpll_data dpll1_dd = { .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, - .clk_bypass = &dpll1_fck, + .clk_bypass_name = "dpll1_fck", .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), @@ -347,7 +343,7 @@ static struct dpll_data dpll2_dd = { .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, - .clk_bypass = &dpll2_fck, + .clk_bypass_name = "dpll2_fck", .clk_ref = &sys_ck, .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), @@ -1077,6 +1073,17 @@ static struct clk dpll1_fck = { .recalc = &omap2_clksel_recalc, }; +static struct clk dpll1_fck_3430es2 = { + .name = "dpll1_fck", + .ops = &clkops_null, + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430ES2_MPU_CLK_SRC_MASK, + .clksel = div4_core_clksel, + .recalc = &omap2_clksel_recalc, +}; + static struct clk mpu_ck = { .name = "mpu_ck", .ops = &clkops_null, @@ -1133,6 +1140,17 @@ static struct clk dpll2_fck = { .recalc = &omap2_clksel_recalc, }; +static struct clk dpll2_fck_3430es2 = { + .name = "dpll2_fck", + .ops = &clkops_null, + .parent = &core_ck, + .init = &omap2_init_clksel_parent, + .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), + .clksel_mask = OMAP3430ES2_IVA2_CLK_SRC_MASK, + .clksel = div4_core_clksel, + .recalc = &omap2_clksel_recalc, +}; + static struct clk iva2_ck = { .name = "iva2_ck", .ops = &clkops_omap2_dflt_wait, @@ -3261,11 +3279,13 @@ static struct omap_clk omap3xxx_clks[] = { CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_3XXX), CLK(NULL, "sys_clkout2", &sys_clkout2, CK_3XXX), CLK(NULL, "corex2_fck", &corex2_fck, CK_3XXX), - CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3XXX), + CLK(NULL, "dpll1_fck", &dpll1_fck, CK_3430ES1), + CLK(NULL, "dpll1_fck", &dpll1_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), CLK(NULL, "mpu_ck", &mpu_ck, CK_3XXX), CLK(NULL, "arm_fck", &arm_fck, CK_3XXX), CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX), - CLK(NULL, "dpll2_fck", &dpll2_fck, CK_34XX | CK_36XX), + CLK(NULL, "dpll2_fck", &dpll2_fck, CK_3430ES1), + CLK(NULL, "dpll2_fck", &dpll2_fck_3430es2, CK_3430ES2PLUS | CK_36XX), CLK(NULL, "iva2_ck", &iva2_ck, CK_34XX | CK_36XX), CLK(NULL, "l3_ick", &l3_ick, CK_3XXX), CLK(NULL, "l4_ick", &l4_ick, CK_3XXX), @@ -3535,6 +3555,9 @@ int __init omap3xxx_clk_init(void) omap2_init_clk_clkdm(c->lk.clk); } + /* Initialise clk pointers for parent/ref/bypass clks */ + omap_init_clk_pts(); + recalculate_root_clocks(); pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n", diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index b912759..fd80872 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -80,6 +80,7 @@ /* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430ES2_IVA2_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 @@ -125,6 +126,7 @@ /* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19) +#define OMAP3430ES2_MPU_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3430_MPU_DPLL_DIV_SHIFT 0