From patchwork Wed Feb 16 13:00:20 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tarun Kanti DebBarma X-Patchwork-Id: 567261 X-Patchwork-Delegate: tony@atomide.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1GCw3V6027726 for ; Wed, 16 Feb 2011 12:58:03 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754379Ab1BPM6B (ORCPT ); Wed, 16 Feb 2011 07:58:01 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:32922 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753974Ab1BPM5y (ORCPT ); Wed, 16 Feb 2011 07:57:54 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p1GCvowt023889 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Wed, 16 Feb 2011 06:57:53 -0600 Received: from localhost.localdomain (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p1GCvk1t014270; Wed, 16 Feb 2011 18:27:50 +0530 (IST) From: Tarun Kanti DebBarma To: linux-omap@vger.kernel.org Cc: khilman@ti.com, Tarun Kanti DebBarma Subject: [PATCH v10 11/11] OMAP: dmtimer: add timeout to low-level routines Date: Wed, 16 Feb 2011 18:30:20 +0530 Message-Id: <1297861220-831-12-git-send-email-tarun.kanti@ti.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1297861220-831-1-git-send-email-tarun.kanti@ti.com> References: <1297861220-831-1-git-send-email-tarun.kanti@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Wed, 16 Feb 2011 12:58:03 +0000 (UTC) diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index fcac422..a39d5ba 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c @@ -43,6 +43,7 @@ #include #include #include +#include /* register offsets */ #define _OMAP_TIMER_ID_OFFSET 0x00 @@ -153,6 +154,8 @@ #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) +#define MAX_WRITE_PEND_WAIT 10000 /* 10ms timeout delay */ + static LIST_HEAD(omap_timer_list); static DEFINE_SPINLOCK(dm_timer_lock); @@ -168,16 +171,23 @@ static DEFINE_SPINLOCK(dm_timer_lock); static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) { struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; + int i = 0; if (reg >= OMAP_TIMER_WAKEUP_EN_REG) reg += pdata->func_offset; else if (reg >= OMAP_TIMER_STAT_REG) reg += pdata->intr_offset; - if (timer->posted) - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) - & (reg >> WPSHIFT)) - cpu_relax(); + if (timer->posted) { + omap_test_timeout(!(readl(timer->io_base + + ((OMAP_TIMER_WRITE_PEND_REG + + pdata->func_offset) & 0xff)) & (reg >> WPSHIFT)), + MAX_WRITE_PEND_WAIT, i); + + if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT)) + pr_err(": read timeout\n"); + } + return readl(timer->io_base + (reg & 0xff)); } @@ -195,16 +205,23 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, u32 value) { struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data; + int i = 0; if (reg >= OMAP_TIMER_WAKEUP_EN_REG) reg += pdata->func_offset; else if (reg >= OMAP_TIMER_STAT_REG) reg += pdata->intr_offset; - if (timer->posted) - while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)) - & (reg >> WPSHIFT)) - cpu_relax(); + if (timer->posted) { + omap_test_timeout(!(readl(timer->io_base + + ((OMAP_TIMER_WRITE_PEND_REG + + pdata->func_offset) & 0xff)) & (reg >> WPSHIFT)), + MAX_WRITE_PEND_WAIT, i); + + if (WARN_ON(i == MAX_WRITE_PEND_WAIT)) + pr_err(": write timeout\n"); + } + writel(value, timer->io_base + (reg & 0xff)); }