From patchwork Sat Feb 19 10:42:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 574561 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1JAguId032649 for ; Sat, 19 Feb 2011 10:43:04 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754116Ab1BSKnB (ORCPT ); Sat, 19 Feb 2011 05:43:01 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:48715 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753975Ab1BSKmx (ORCPT ); Sat, 19 Feb 2011 05:42:53 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p1JAggm7025989 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 19 Feb 2011 04:42:44 -0600 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p1JAgfro013934; Sat, 19 Feb 2011 16:12:41 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id p1JAge9F028581; Sat, 19 Feb 2011 16:12:40 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id p1JAgerO028579; Sat, 19 Feb 2011 16:12:40 +0530 From: Santosh Shilimkar To: linux-omap@vger.kernel.org Cc: khilman@ti.com, linux-arm-kernel@lists.infradead.org, Santosh Shilimkar Subject: [PATCH 07/17] omap4: pm: CPU1 wakeup workaround form Low power modes Date: Sat, 19 Feb 2011 16:12:28 +0530 Message-Id: <1298112158-28469-8-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1298112158-28469-1-git-send-email-santosh.shilimkar@ti.com> References: <1298112158-28469-1-git-send-email-santosh.shilimkar@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sat, 19 Feb 2011 10:43:04 +0000 (UTC) diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c index 9f8f097..cf4ab15 100644 --- a/arch/arm/mach-omap2/omap-hotplug.c +++ b/arch/arm/mach-omap2/omap-hotplug.c @@ -23,6 +23,7 @@ #include #include "powerdomain.h" +#include "clockdomain.h" int platform_cpu_kill(unsigned int cpu) { @@ -36,6 +37,11 @@ int platform_cpu_kill(unsigned int cpu) void platform_cpu_die(unsigned int cpu) { unsigned int this_cpu; + static struct clockdomain *cpu1_clkdm; + + /* To avoid cpu1 clockdomain lookup every time */ + if (!cpu1_clkdm) + cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); flush_cache_all(); dsb(); @@ -59,6 +65,9 @@ void platform_cpu_die(unsigned int cpu) * OK, proper wakeup, we're done */ omap_wakeupgen_irqmask_all(this_cpu, 0); + + /* Restore clockdomain to hardware supervised */ + clkdm_allow_idle(cpu1_clkdm); break; } pr_debug("CPU%u: spurious wakeup call\n", cpu); diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index b105a29..31c9b79 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -25,6 +25,8 @@ #include #include +#include "clockdomain.h" + /* SCU base address */ void __iomem *scu_base; @@ -48,6 +50,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) { + static struct clockdomain *cpu1_clkdm; + static bool booted; /* * Set synchronisation state between this boot processor * and the secondary one @@ -63,7 +67,28 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) omap_modify_auxcoreboot0(0x200, 0xfffffdff); flush_cache_all(); smp_wmb(); - smp_cross_call(cpumask_of(cpu), 1); + + /* To avoid cpu1 clockdomain lookup every time */ + if (!cpu1_clkdm) + cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); + + /* + * The SGI(Software Generated Interrupts) are not wakeup capable + * from low power states. This is known limitation on OMAP4 and + * needs to be worked around by using software forced clockdomain + * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to + * software force wakeup. After the wakeup, CPU1 restores its + * clockdomain hardware supervised mode. + * More details can be found in OMAP4430 TRM - Version J + * Section : + * 4.3.4.2 Power States of CPU0 and CPU1 + */ + if (booted) { + clkdm_wakeup(cpu1_clkdm); + } else { + dsb_sev(); + booted = true; + } /* * Now the secondary core is starting up let it run its