From patchwork Mon Feb 21 13:46:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Santosh Shilimkar X-Patchwork-Id: 577571 X-Patchwork-Delegate: khilman@deeprootsystems.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p1LDkcou004726 for ; Mon, 21 Feb 2011 13:46:43 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756058Ab1BUNqi (ORCPT ); Mon, 21 Feb 2011 08:46:38 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:37905 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756034Ab1BUNqg (ORCPT ); Mon, 21 Feb 2011 08:46:36 -0500 Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p1LDkXYU017269 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 21 Feb 2011 07:46:35 -0600 Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p1LDkVd8013535; Mon, 21 Feb 2011 19:16:31 +0530 (IST) Received: from linfarm476.india.ti.com (localhost [127.0.0.1]) by linfarm476.india.ti.com (8.12.11/8.12.11) with ESMTP id p1LDkVqK001117; Mon, 21 Feb 2011 19:16:31 +0530 Received: (from a0393909@localhost) by linfarm476.india.ti.com (8.12.11/8.12.11/Submit) id p1LDkUwE001115; Mon, 21 Feb 2011 19:16:30 +0530 From: Santosh Shilimkar To: linux-omap@vger.kernel.org Cc: balbi@ti.com, b-cousson@ti.com, r.sricharan@ti.com, Santosh Shilimkar Subject: [PATCH 3/6] omap3: l3: Introduce l3-interconnect error handling driver Date: Mon, 21 Feb 2011 19:16:27 +0530 Message-Id: <1298295990-1070-4-git-send-email-santosh.shilimkar@ti.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <1298295990-1070-1-git-send-email-santosh.shilimkar@ti.com> References: <1298295990-1070-1-git-send-email-santosh.shilimkar@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 21 Feb 2011 13:46:43 +0000 (UTC) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 4ab82f6..623aee1 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -135,6 +135,9 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o +# L3 interconnect +obj-$(CONFIG_ARCH_OMAP3) += l3_interconnect_3xxx.o + obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o mailbox_mach-objs := mailbox.o diff --git a/arch/arm/mach-omap2/l3_interconnect_3xxx.c b/arch/arm/mach-omap2/l3_interconnect_3xxx.c new file mode 100644 index 0000000..1d1aae3 --- /dev/null +++ b/arch/arm/mach-omap2/l3_interconnect_3xxx.c @@ -0,0 +1,314 @@ + /* + * L3 Interconnect Driver + * + * Copyright (C) 2011 Texas Corporation + * Felipe Balbi + * Santosh Shilimkar + * Sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ + +#include +#include +#include +#include +#include +#include "l3_interconnect_3xxx.h" + +static inline u64 omap3_l3_readll(void __iomem *base, u16 reg) +{ + return __raw_readll(base + reg); +} + +static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value) +{ + __raw_writell(value, base + reg); +} + +static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error) +{ + return (error & 0x0f000000) >> L3_ERROR_LOG_CODE; +} + +static inline u32 omap3_l3_decode_addr(u64 error_addr) +{ + return error_addr & 0xffffffff; +} + +static inline unsigned omap3_l3_decode_cmd(u64 error) +{ + return (error & 0x07) >> L3_ERROR_LOG_CMD; +} + +static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error) +{ + return (error & 0xff00) >> L3_ERROR_LOG_INITID; +} + +static inline unsigned omap3_l3_decode_req_info(u64 error) +{ + return (error >> 32) & 0xffff; +} + +static char *omap3_l3_code_string(u8 code) +{ + switch (code) { + case OMAP_L3_CODE_NOERROR: + return "No Error"; + case OMAP_L3_CODE_UNSUP_CMD: + return "Unsupported Command"; + case OMAP_L3_CODE_ADDR_HOLE: + return "Address Hole"; + case OMAP_L3_CODE_PROTECT_VIOLATION: + return "Protection Violation"; + case OMAP_L3_CODE_IN_BAND_ERR: + return "In-band Error"; + case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT: + return "Request Timeout Not Accepted"; + case OMAP_L3_CODE_REQ_TOUT_NO_RESP: + return "Request Timeout, no response"; + default: + return "UNKNOWN error"; + } +} + +static char *omap3_l3_initiator_string(u8 initid) +{ + switch (initid) { + case OMAP_L3_LCD: + return "LCD"; + case OMAP_L3_SAD2D: + return "SAD2D"; + case OMAP_L3_IA_MPU_SS_1: + case OMAP_L3_IA_MPU_SS_2: + case OMAP_L3_IA_MPU_SS_3: + case OMAP_L3_IA_MPU_SS_4: + case OMAP_L3_IA_MPU_SS_5: + return "MPU"; + case OMAP_L3_IA_IVA_SS_1: + case OMAP_L3_IA_IVA_SS_2: + case OMAP_L3_IA_IVA_SS_3: + return "IVA_SS"; + case OMAP_L3_IA_IVA_SS_DMA_1: + case OMAP_L3_IA_IVA_SS_DMA_2: + case OMAP_L3_IA_IVA_SS_DMA_3: + case OMAP_L3_IA_IVA_SS_DMA_4: + case OMAP_L3_IA_IVA_SS_DMA_5: + case OMAP_L3_IA_IVA_SS_DMA_6: + return "IVA_SS_DMA"; + case OMAP_L3_IA_SGX: + return "SGX"; + case OMAP_L3_IA_CAM_1: + case OMAP_L3_IA_CAM_2: + case OMAP_L3_IA_CAM_3: + return "CAM"; + case OMAP_L3_IA_DAP: + return "DAP"; + case OMAP_L3_SDMA_WR_1: + case OMAP_L3_SDMA_WR_2: + return "SDMA_WR"; + case OMAP_L3_SDMA_RD_1: + case OMAP_L3_SDMA_RD_2: + case OMAP_L3_SDMA_RD_3: + case OMAP_L3_SDMA_RD_4: + return "SDMA_RD"; + case OMAP_L3_USBOTG: + return "USB_OTG"; + case OMAP_L3_USBHOST: + return "USB_HOST"; + default: + return "UNKNOWN Initiator"; + } +} + +/** + * omap3_l3_block_irq - handles a register block's irq + * @l3: struct omap3_l3 * + * @base: register block base address + * @error: L3_ERROR_LOG register of our block + * + * Called in hard-irq context. Caller should take care of locking + * + * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error + * Analysis Sequence, we are following that sequence here, please + * refer to that Figure for more information on the subject. + */ +static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, + u64 error, int error_addr) +{ + u8 code = omap3_l3_decode_error_code(error); + u8 initid = omap3_l3_decode_initid(error); + u8 multi = error & L3_ERROR_LOG_MULTI; + u32 address = omap3_l3_decode_addr(error_addr); + + WARN(true, "%s Error seen by %s %s at address %x\n", + omap3_l3_code_string(code), + omap3_l3_initiator_string(initid), + multi ? "Multiple Errors" : "", + address); + + return IRQ_HANDLED; +} + +static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) +{ + struct omap3_l3 *l3 = _l3; + + u64 status, clear; + u64 error; + u64 error_addr; + u64 err_source = 0; + void __iomem *base; + int int_type; + + irqreturn_t ret = IRQ_NONE; + + if (irq == l3->app_irq) + int_type = L3_APPLICATION_ERROR; + else + int_type = L3_DEBUG_ERROR; + + if (!int_type) { + status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); + /* + * if we have a timeout error, there's nothing we can + * do besides rebooting the board. So let's BUG on any + * of such errors and handle the others. timeout error + * is severe and not expected to occur. + */ + BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK); + } else { + status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); + /* No timeout error for debug sources */ + } + + base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source))); + + /* identify the error source */ + for (err_source = 0; !(status & (1 << err_source)); err_source++) + ; + error = omap3_l3_readll(base, L3_ERROR_LOG); + + if (error) { + error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); + + ret |= omap3_l3_block_irq(l3, error, error_addr); + } + + /* Clear the status register */ + clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) | + (L3_AGENT_STATUS_CLEAR_TA)); + + omap3_l3_writell(base, L3_AGENT_STATUS, clear); + + /* clear the error log register */ + omap3_l3_writell(base, L3_ERROR_LOG, error); + + return ret; +} + +static int __init omap3_l3_probe(struct platform_device *pdev) +{ + struct omap3_l3 *l3; + struct resource *res; + int ret; + int irq; + + l3 = kzalloc(sizeof(*l3), GFP_KERNEL); + if (!l3) { + ret = -ENOMEM; + goto err0; + } + + platform_set_drvdata(pdev, l3); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "couldn't find resource\n"); + ret = -ENODEV; + goto err1; + } + l3->rt = ioremap(res->start, resource_size(res)); + if (!(l3->rt)) { + dev_err(&pdev->dev, "ioremap failed\n"); + ret = -ENOMEM; + goto err2; + } + + irq = platform_get_irq(pdev, 0); + ret = request_irq(irq, omap3_l3_app_irq, + IRQF_DISABLED | IRQF_TRIGGER_RISING, + "l3-debug-irq", l3); + if (ret) { + dev_err(&pdev->dev, "couldn't request debug irq\n"); + goto err3; + } + l3->debug_irq = irq; + + irq = platform_get_irq(pdev, 1); + ret = request_irq(irq, omap3_l3_app_irq, + IRQF_DISABLED | IRQF_TRIGGER_RISING, + "l3-app-irq", l3); + + if (ret) { + dev_err(&pdev->dev, "couldn't request app irq\n"); + goto err4; + } + + l3->app_irq = irq; + goto err0; + +err4: +err3: + iounmap(l3->rt); +err2: +err1: + kfree(l3); +err0: + return ret; +} + +static int __exit omap3_l3_remove(struct platform_device *pdev) +{ + struct omap3_l3 *l3 = platform_get_drvdata(pdev); + + free_irq(l3->app_irq, l3); + free_irq(l3->debug_irq, l3); + iounmap(l3->rt); + kfree(l3); + + return 0; +} + +static struct platform_driver omap3_l3_driver = { + .remove = __exit_p(omap3_l3_remove), + .driver = { + .name = "omap3-l3-interconnect", + }, +}; + +static int __init omap3_l3_init(void) +{ + return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe); +} +postcore_initcall_sync(omap3_l3_init); + +static void __exit omap3_l3_exit(void) +{ + platform_driver_unregister(&omap3_l3_driver); +} +module_exit(omap3_l3_exit); diff --git a/arch/arm/mach-omap2/l3_interconnect_3xxx.h b/arch/arm/mach-omap2/l3_interconnect_3xxx.h new file mode 100644 index 0000000..d04db61 --- /dev/null +++ b/arch/arm/mach-omap2/l3_interconnect_3xxx.h @@ -0,0 +1,338 @@ + /* + * L3 Interconnect Driver header + * + * Copyright (C) 2011 Texas Corporation + * Felipe Balbi + * Santosh Shilimkar + * sricharan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H +#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H + +/* Register definitions. All 64-bit wide */ +#define L3_COMPONENT 0x000 +#define L3_CORE 0x018 +#define L3_AGENT_CONTROL 0x020 +#define L3_AGENT_STATUS 0x028 +#define L3_ERROR_LOG 0x058 + +#define L3_ERROR_LOG_MULTI (1 << 31) +#define L3_ERROR_LOG_SECONDARY (1 << 30) + +#define L3_ERROR_LOG_ADDR 0x060 + +/* Register definitions for Sideband Interconnect */ +#define L3_SI_CONTROL 0x020 +#define L3_SI_FLAG_STATUS_0 0x510 + +const u64 shift = 1; + +#define L3_STATUS_0_MPUIA_BRST (shift << 0) +#define L3_STATUS_0_MPUIA_RSP (shift << 1) +#define L3_STATUS_0_MPUIA_INBAND (shift << 2) +#define L3_STATUS_0_IVAIA_BRST (shift << 6) +#define L3_STATUS_0_IVAIA_RSP (shift << 7) +#define L3_STATUS_0_IVAIA_INBAND (shift << 8) +#define L3_STATUS_0_SGXIA_BRST (shift << 9) +#define L3_STATUS_0_SGXIA_RSP (shift << 10) +#define L3_STATUS_0_SGXIA_MERROR (shift << 11) +#define L3_STATUS_0_CAMIA_BRST (shift << 12) +#define L3_STATUS_0_CAMIA_RSP (shift << 13) +#define L3_STATUS_0_CAMIA_INBAND (shift << 14) +#define L3_STATUS_0_DISPIA_BRST (shift << 15) +#define L3_STATUS_0_DISPIA_RSP (shift << 16) +#define L3_STATUS_0_DMARDIA_BRST (shift << 18) +#define L3_STATUS_0_DMARDIA_RSP (shift << 19) +#define L3_STATUS_0_DMAWRIA_BRST (shift << 21) +#define L3_STATUS_0_DMAWRIA_RSP (shift << 22) +#define L3_STATUS_0_USBOTGIA_BRST (shift << 24) +#define L3_STATUS_0_USBOTGIA_RSP (shift << 25) +#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26) +#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27) +#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28) +#define L3_STATUS_0_SMSTA_REQ (shift << 48) +#define L3_STATUS_0_GPMCTA_REQ (shift << 49) +#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50) +#define L3_STATUS_0_OCMROMTA_REQ (shift << 51) +#define L3_STATUS_0_IVATA_REQ (shift << 54) +#define L3_STATUS_0_SGXTA_REQ (shift << 55) +#define L3_STATUS_0_SGXTA_SERROR (shift << 56) +#define L3_STATUS_0_GPMCTA_SERROR (shift << 57) +#define L3_STATUS_0_L4CORETA_REQ (shift << 58) +#define L3_STATUS_0_L4PERTA_REQ (shift << 59) +#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) +#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) + +#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ + | L3_STATUS_0_MPUIA_RSP \ + | L3_STATUS_0_IVAIA_BRST \ + | L3_STATUS_0_IVAIA_RSP \ + | L3_STATUS_0_SGXIA_BRST \ + | L3_STATUS_0_SGXIA_RSP \ + | L3_STATUS_0_CAMIA_BRST \ + | L3_STATUS_0_CAMIA_RSP \ + | L3_STATUS_0_DISPIA_BRST \ + | L3_STATUS_0_DISPIA_RSP \ + | L3_STATUS_0_DMARDIA_BRST \ + | L3_STATUS_0_DMARDIA_RSP \ + | L3_STATUS_0_DMAWRIA_BRST \ + | L3_STATUS_0_DMAWRIA_RSP \ + | L3_STATUS_0_USBOTGIA_BRST \ + | L3_STATUS_0_USBOTGIA_RSP \ + | L3_STATUS_0_USBHOSTIA_BRST \ + | L3_STATUS_0_SMSTA_REQ \ + | L3_STATUS_0_GPMCTA_REQ \ + | L3_STATUS_0_OCMRAMTA_REQ \ + | L3_STATUS_0_OCMROMTA_REQ \ + | L3_STATUS_0_IVATA_REQ \ + | L3_STATUS_0_SGXTA_REQ \ + | L3_STATUS_0_L4CORETA_REQ \ + | L3_STATUS_0_L4PERTA_REQ \ + | L3_STATUS_0_L4EMUTA_REQ \ + | L3_STATUS_0_MAD2DTA_REQ) + +#define L3_SI_FLAG_STATUS_1 0x530 + +#define L3_STATUS_1_MPU_DATAIA (1 << 0) +#define L3_STATUS_1_DAPIA0 (1 << 3) +#define L3_STATUS_1_DAPIA1 (1 << 4) +#define L3_STATUS_1_IVAIA (1 << 6) + +#define L3_PM_ERROR_LOG 0x020 +#define L3_PM_CONTROL 0x028 +#define L3_PM_ERROR_CLEAR_SINGLE 0x030 +#define L3_PM_ERROR_CLEAR_MULTI 0x038 +#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n)) +#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n)) +#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n)) +#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n)) + +/* L3 error log bit fields. Common for IA and TA */ +#define L3_ERROR_LOG_CODE 24 +#define L3_ERROR_LOG_INITID 8 +#define L3_ERROR_LOG_CMD 0 + +/* L3 agent status bit fields. */ +#define L3_AGENT_STATUS_CLEAR_IA 0x10000000 +#define L3_AGENT_STATUS_CLEAR_TA 0x01000000 + +#define OMAP34xx_IRQ_L3_APP 10 +#define L3_APPLICATION_ERROR 0x0 +#define L3_DEBUG_ERROR 0x1 + +enum omap3_l3_initiator_id { + /* LCD has 1 ID */ + OMAP_L3_LCD = 29, + /* SAD2D has 1 ID */ + OMAP_L3_SAD2D = 28, + /* MPU has 5 IDs */ + OMAP_L3_IA_MPU_SS_1 = 27, + OMAP_L3_IA_MPU_SS_2 = 26, + OMAP_L3_IA_MPU_SS_3 = 25, + OMAP_L3_IA_MPU_SS_4 = 24, + OMAP_L3_IA_MPU_SS_5 = 23, + /* IVA2.2 SS has 3 IDs*/ + OMAP_L3_IA_IVA_SS_1 = 22, + OMAP_L3_IA_IVA_SS_2 = 21, + OMAP_L3_IA_IVA_SS_3 = 20, + /* IVA 2.2 SS DMA has 6 IDS */ + OMAP_L3_IA_IVA_SS_DMA_1 = 19, + OMAP_L3_IA_IVA_SS_DMA_2 = 18, + OMAP_L3_IA_IVA_SS_DMA_3 = 17, + OMAP_L3_IA_IVA_SS_DMA_4 = 16, + OMAP_L3_IA_IVA_SS_DMA_5 = 15, + OMAP_L3_IA_IVA_SS_DMA_6 = 14, + /* SGX has 1 ID */ + OMAP_L3_IA_SGX = 13, + /* CAM has 3 ID */ + OMAP_L3_IA_CAM_1 = 12, + OMAP_L3_IA_CAM_2 = 11, + OMAP_L3_IA_CAM_3 = 10, + /* DAP has 1 ID */ + OMAP_L3_IA_DAP = 9, + /* SDMA WR has 2 IDs */ + OMAP_L3_SDMA_WR_1 = 8, + OMAP_L3_SDMA_WR_2 = 7, + /* SDMA RD has 4 IDs */ + OMAP_L3_SDMA_RD_1 = 6, + OMAP_L3_SDMA_RD_2 = 5, + OMAP_L3_SDMA_RD_3 = 4, + OMAP_L3_SDMA_RD_4 = 3, + /* HSUSB OTG has 1 ID */ + OMAP_L3_USBOTG = 2, + /* HSUSB HOST has 1 ID */ + OMAP_L3_USBHOST = 1, +}; + +enum omap3_l3_code { + OMAP_L3_CODE_NOERROR = 0, + OMAP_L3_CODE_UNSUP_CMD = 1, + OMAP_L3_CODE_ADDR_HOLE = 2, + OMAP_L3_CODE_PROTECT_VIOLATION = 3, + OMAP_L3_CODE_IN_BAND_ERR = 4, + /* codes 5 and 6 are reserved */ + OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7, + OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8, + /* codes 9 - 15 are also reserved */ +}; + +struct omap3_l3 { + struct device *dev; + struct clk *ick; + + /* memory base*/ + void __iomem *rt; + + int debug_irq; + int app_irq; + + /* true when and inband functional error occurs */ + unsigned inband:1; +}; + +/* offsets for l3 agents in order with the Flag status register */ +unsigned int __iomem omap3_l3_app_bases[] = { + /* MPU IA */ + 0x1400, + 0x1400, + 0x1400, + /* RESERVED */ + 0, + 0, + 0, + /* IVA 2.2 IA */ + 0x1800, + 0x1800, + 0x1800, + /* SGX IA */ + 0x1c00, + 0x1c00, + /* RESERVED */ + 0, + /* CAMERA IA */ + 0x5800, + 0x5800, + 0x5800, + /* DISPLAY IA */ + 0x5400, + 0x5400, + /* RESERVED */ + 0, + /*SDMA RD IA */ + 0x4c00, + 0x4c00, + /* RESERVED */ + 0, + /* SDMA WR IA */ + 0x5000, + 0x5000, + /* RESERVED */ + 0, + /* USB OTG IA */ + 0x4400, + 0x4400, + 0x4400, + /* USB HOST IA */ + 0x4000, + 0x4000, + /* RESERVED */ + 0, + 0, + 0, + 0, + /* SAD2D IA */ + 0x3000, + 0x3000, + 0x3000, + /* RESERVED */ + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + /* SMA TA */ + 0x2000, + /* GPMC TA */ + 0x2400, + /* OCM RAM TA */ + 0x2800, + /* OCM ROM TA */ + 0x2C00, + /* L4 CORE TA */ + 0x6800, + /* L4 PER TA */ + 0x6c00, + /* IVA 2.2 TA */ + 0x6000, + /* SGX TA */ + 0x6400, + /* L4 EMU TA */ + 0x7000, + /* GPMC TA */ + 0x2400, + /* L4 CORE TA */ + 0x6800, + /* L4 PER TA */ + 0x6c00, + /* L4 EMU TA */ + 0x7000, + /* MAD2D TA */ + 0x3400, + /* RESERVED */ + 0, + 0, +}; + +unsigned int __iomem omap3_l3_debug_bases[] = { + /* MPU DATA IA */ + 0x1400, + /* RESERVED */ + 0, + 0, + /* DAP IA */ + 0x5c00, + 0x5c00, + /* RESERVED */ + 0, + /* IVA 2.2 IA */ + 0x1800, + /* REST RESERVED */ +}; + +u32 *omap3_l3_bases[] = { + omap3_l3_app_bases, + omap3_l3_debug_bases, +}; + +/* + * REVISIT define __raw_readll/__raw_writell here, but move them to + * at some point + */ +#define __raw_writell(v, a) (__chk_io_ptr(a), \ + *(volatile u64 __force *)(a) = (v)) +#define __raw_readll(a) (__chk_io_ptr(a), \ + *(volatile u64 __force *)(a)) + +#endif